component
TPS2320IPWR
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS2320IPWR
Texas Instruments · Supervisor And Reset ICs · TSSOP-16
TPS2320IPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GATE1 | output | Gate drive output for channel 1 high-side MOSFET, 10-20 µA source and 50-100 µA sink current, 9-12 V gate-to-source clamp, 30 V maximum rating. |
| 2 | GATE2 | output | Gate drive output for channel 2 high-side MOSFET, 10-20 µA source and 50-100 µA sink current, 9-12 V gate-to-source clamp, 22 V maximum rating. |
| 3 | DGND | power_in | Digital ground reference, connect to AGND as close as possible. |
| 4 | TIMER | output | Overcurrent timing node with 50 µA charge current and 2.5 mA discharge current, capacitor charging to 0.5 V threshold triggers circuit-breaker latch. |
| 5 | VREG | power_out | Regulated 3.5-5.5 V regulator output powered from IN1, requires 0.1 µF bypass capacitor to ground for stable operation. |
| 6 | AGND | power_in | Analog ground reference, connect to DGND as close as possible. |
| 7 | ISENSE2 | input | Channel 2 current-sense input connected to voltage across sense resistor between IN2 and MOSFET drain, voltage must not exceed VI(IN2). |
| 8 | ISENSE1 | input | Channel 1 current-sense input connected to voltage across sense resistor between IN1 and MOSFET drain, voltage must not exceed VI(IN1). |
| 9 | IN1 | power_in | Primary power input 3-13 V, supplies device operating current for both channels and feeds internal LDO for VREG regulator. |
| 10 | IN2 | power_in | Secondary power input 3-5.5 V for channel 2 only, independent power rail from IN1. |
| 11 | ISET2 | input | Channel 2 current-limit setting input, external resistor to IN2 sets overcurrent threshold with 50 µA internal current source pulldown. |
| 12 | ISET1 | input | Channel 1 current-limit setting input, external resistor to IN1 sets overcurrent threshold with 50 µA internal current source pulldown. |
| 13 | FAULT | output | Open-drain overcurrent fault output pulled low when overcurrent condition persists until TIMER reaches 0.5 V, latches until device reset or enable toggle. |
| 14 | ENABLE | input | Active-low TTL/CMOS compatible enable input for TPS2320, 2 V high threshold and 0.8 V low threshold, disables gates when pulled high. |
| 15 | DISCH2 | output | Channel 2 discharge transistor output connected to external MOSFET source, provides gate voltage clamping reference and 10 mA discharge current for load capacitance. |
| 16 | DISCH1 | output | Channel 1 discharge transistor output connected to external MOSFET source, provides gate voltage clamping reference and 10 mA discharge current for load capacitance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
TPS2320IPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
tps2320ipwr-etched.step/tps2320ipwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps2320ipwr.step/tps2320ipwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
0c4eed4165426632, retrieved 2026-09-24, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).