component
TPS2112APWR
Public Made by Adomby adom
Texas Instruments Monitors & Reset Circuits, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+44@@ -0,0 +1,44 @@+# TPS2112APWR++**Texas Instruments** · Monitors & Reset Circuits · TSSOP-8++TPS2112APWR from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | STAT | output | STAT is an open-drain status output that is Hi-Z when the IN2 switch is on and pulls low when the IN1 switch is on or OUT is Hi-Z (EN = logic 0), with a saturation voltage of 0.4 V max at 2 mA sink current and a 5.5 V max output voltage. |+| 2 | EN | input | TTL- and CMOS-compatible enable input with a 1-μA pull-up, where logic 1 (VIH min 2 V) disables the power switch and sets OUT to Hi-Z, and logic 0 (VIL max 0.7 V) enables automatic switching. |+| 3 | VSNS | input | Logic input with a 0 to 5.5 V range whose threshold of 0.8 V selects IN1 as the output when above it, otherwise OUT connects to the higher of IN1 and IN2. |+| 4 | ILIM | input | A resistor from ILIM to GND sets the current limit to 250/RILIM A for TPS2112A or 500/RILIM A for TPS2113A, and RILIM equal to zero is not recommended because it disables current limiting. |+| 5 | GND | power_in | Power ground; all device voltages are specified with respect to this pin. |+| 6 | IN2 | input | Secondary power switch input that can be enabled only when the IN2 supply is above its UVLO threshold and at least one supply exceeds the internal VDD UVLO, with 1.5 V to 5.5 V recommended operating range when IN1 is at or above 2.8 V. |+| 7 | OUT | output | Power switch output that connects to IN1 or IN2 per the VSNS and comparator logic, with a continuous output current rating of 0.9 A for the TPS2112APW. |+| 8 | IN1 | input | Primary power switch input that can be enabled only when the IN1 supply is above its UVLO threshold and at least one supply exceeds the internal VDD UVLO, with 1.5 V to 5.5 V recommended operating range when IN2 is at or above 2.8 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-8 |+| Category | Power Supply Chip |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `TPS2112APWR`+- Footprint: `Package_SO:TSSOP-8_3x3mm_P0.65mm`+- 3D model: TSSOP-8 (KiCad packages3D, STEP)+- 3D model files: `tps2112apwr-etched.step` / `tps2112apwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps2112apwr.step` / `tps2112apwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps2112a.pdf) (31 pp, sha256 `a29cac2ebea4a104`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps2112apwr-datasheet.pdf)
page.jsonadded+200@@ -0,0 +1,200 @@+{+ "slug": "tps2112apwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Monitors & Reset Circuits, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power supply chip",+ "tps2112apwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps2112apwr.kicad_sym",+ "tps2112apwr.kicad_mod",+ "tps2112apwr.glb",+ "tps2112apwr.step",+ "tps2112apwr.lbr",+ "docs/hero.png",+ "docs/tps2112apwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps2112apwr-hero.glb",+ "tps2112apwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS2112APWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-8",+ "pin_count": 8,+ "category": "Power Supply Chip",+ "subcategory": "Monitors & Reset Circuits",+ "datasheet": "https://www.ti.com/lit/ds/symlink/tps2112a.pdf",+ "parts": {+ "symbol": "tps2112apwr.kicad_sym",+ "footprint": "tps2112apwr.kicad_mod",+ "model_3d": "tps2112apwr-hero.glb",+ "model_3d_plain": "tps2112apwr.glb",+ "model_3d_step": "tps2112apwr-etched.step",+ "model_3d_step_plain": "tps2112apwr.step",+ "lbr": "tps2112apwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2649433",+ "digikey": "296-16937-2-ND",+ "mouser": "595-TPS2112APWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:44:31Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-16937-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS2112APWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "STAT",+ "type": "output",+ "description": "STAT is an open-drain status output that is Hi-Z when the IN2 switch is on and pulls low when the IN1 switch is on or OUT is Hi-Z (EN = logic 0), with a saturation voltage of 0.4 V max at 2 mA sink current and a 5.5 V max output voltage."+ },+ {+ "number": "2",+ "name": "EN",+ "type": "input",+ "description": "TTL- and CMOS-compatible enable input with a 1-μA pull-up, where logic 1 (VIH min 2 V) disables the power switch and sets OUT to Hi-Z, and logic 0 (VIL max 0.7 V) enables automatic switching."+ },+ {+ "number": "3",+ "name": "VSNS",+ "type": "input",+ "description": "Logic input with a 0 to 5.5 V range whose threshold of 0.8 V selects IN1 as the output when above it, otherwise OUT connects to the higher of IN1 and IN2."+ },+ {+ "number": "4",+ "name": "ILIM",+ "type": "input",+ "description": "A resistor from ILIM to GND sets the current limit to 250/RILIM A for TPS2112A or 500/RILIM A for TPS2113A, and RILIM equal to zero is not recommended because it disables current limiting."+ },+ {+ "number": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Power ground; all device voltages are specified with respect to this pin."+ },+ {+ "number": "6",+ "name": "IN2",+ "type": "input",+ "description": "Secondary power switch input that can be enabled only when the IN2 supply is above its UVLO threshold and at least one supply exceeds the internal VDD UVLO, with 1.5 V to 5.5 V recommended operating range when IN1 is at or above 2.8 V."+ },+ {+ "number": "7",+ "name": "OUT",+ "type": "output",+ "description": "Power switch output that connects to IN1 or IN2 per the VSNS and comparator logic, with a continuous output current rating of 0.9 A for the TPS2112APW."+ },+ {+ "number": "8",+ "name": "IN1",+ "type": "input",+ "description": "Primary power switch input that can be enabled only when the IN1 supply is above its UVLO threshold and at least one supply exceeds the internal VDD UVLO, with 1.5 V to 5.5 V recommended operating range when IN2 is at or above 2.8 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pinout is shared by the TPS2112A and TPS2113A PW (TSSOP-8) variants; pin numbers and functions are t; Pin types follow the datasheet I/O column: IN1, IN2, EN, VSNS, ILIM are 'input' and OUT and STAT are; The TSSOP-8 pinout has no exposed thermal pad (the Pad entry in Table 1 applies to the DRB SON-8 pac"+ ],+ "pages_sent": 31,+ "cost_usd": 0.1074,+ "at": "2026-10-08T15:44:12"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/tps2112a.pdf",+ "pages": 31,+ "sha256": "a29cac2ebea4a104",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps2112apwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4.9,+ 3,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "cf28a51742b2e31065e201d1b313207140cbfb49062efd938788f7a310d02738",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps2112apwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4.9,+ 3,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d63a57039b63f7b5b146940be9871d6e7c863676c168956b4cec0e82db80697f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}