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TPS2112APWR
Public Made by Adomby adom
Texas Instruments Monitors & Reset Circuits, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS2112APWR
Texas Instruments · Monitors & Reset Circuits · TSSOP-8
TPS2112APWR from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STAT | output | STAT is an open-drain status output that is Hi-Z when the IN2 switch is on and pulls low when the IN1 switch is on or OUT is Hi-Z (EN = logic 0), with a saturation voltage of 0.4 V max at 2 mA sink current and a 5.5 V max output voltage. |
| 2 | EN | input | TTL- and CMOS-compatible enable input with a 1-μA pull-up, where logic 1 (VIH min 2 V) disables the power switch and sets OUT to Hi-Z, and logic 0 (VIL max 0.7 V) enables automatic switching. |
| 3 | VSNS | input | Logic input with a 0 to 5.5 V range whose threshold of 0.8 V selects IN1 as the output when above it, otherwise OUT connects to the higher of IN1 and IN2. |
| 4 | ILIM | input | A resistor from ILIM to GND sets the current limit to 250/RILIM A for TPS2112A or 500/RILIM A for TPS2113A, and RILIM equal to zero is not recommended because it disables current limiting. |
| 5 | GND | power_in | Power ground; all device voltages are specified with respect to this pin. |
| 6 | IN2 | input | Secondary power switch input that can be enabled only when the IN2 supply is above its UVLO threshold and at least one supply exceeds the internal VDD UVLO, with 1.5 V to 5.5 V recommended operating range when IN1 is at or above 2.8 V. |
| 7 | OUT | output | Power switch output that connects to IN1 or IN2 per the VSNS and comparator logic, with a continuous output current rating of 0.9 A for the TPS2112APW. |
| 8 | IN1 | input | Primary power switch input that can be enabled only when the IN1 supply is above its UVLO threshold and at least one supply exceeds the internal VDD UVLO, with 1.5 V to 5.5 V recommended operating range when IN2 is at or above 2.8 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | Power Supply Chip |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPS2112APWR - Footprint:
Package_SO:TSSOP-8_3x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
tps2112apwr-etched.step/tps2112apwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps2112apwr.step/tps2112apwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
a29cac2ebea4a104, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).