component
TPS2069CDGNR-2
Public Made by Adomby adom
Texas Instruments Power Distribution Switches, MSOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
TPS2069CDGNR-2
Texas Instruments · Power Distribution Switches · MSOP-8-EP
TPS2069CDGNR-2 from Texas Instruments, in a MSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device ground connection and return path |
| 2 | IN | power_in | Supply voltage input and internal MOSFET drain; 0.1µF or larger ceramic bypass capacitor required between IN and GND |
| 3 | IN | power_in | Supply voltage input and internal MOSFET drain; 0.1µF or larger ceramic bypass capacitor required between IN and GND |
| 4 | EN/EN | input | Logic input for power switch enable control; logic high level activates the switch |
| 5 | FLT | output | Low-level-active open-drain fault output; asserted when overcurrent or overheating conditions occur |
| 6 | OUT | power_out | Power switch output; supplies current to load |
| 7 | OUT | power_out | Power switch output; supplies current to load |
| 8 | OUT | power_out | Power switch output; supplies current to load |
| 9 | PowerPad | power_in | Exposed pad internally connected to GND; solder to ground plane or PCB ground layer to reduce thermal resistance and junction temperature |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | MSOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
CAD (KiCad official)
- Symbol:
TPS2069CDGNR-2 - Footprint:
Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.5x1.8mm - 3D model: MSOP-8-EP (KiCad packages3D, STEP)
- Annotated 3D hero:
tps2069cdgnr-2-hero.glb(dashed pad outlines, silkscreen with pin 1, signal names; the adom-hero standard) is what the viewer shows. Downloads and EDA use the clean model,tps2069cdgnr-2-etched.glb. - 3D model files:
tps2069cdgnr-2-etched.step/tps2069cdgnr-2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps2069cdgnr-2.step/tps2069cdgnr-2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
8d24f6ead5b760bb, retrieved 2026-10-02, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS2069CDGNR-2
**Texas Instruments** · Power Distribution Switches · MSOP-8-EP
TPS2069CDGNR-2 from Texas Instruments, in a MSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device ground connection and return path |
| 2 | IN | power_in | Supply voltage input and internal MOSFET drain; 0.1µF or larger ceramic bypass capacitor required between IN and GND |
| 3 | IN | power_in | Supply voltage input and internal MOSFET drain; 0.1µF or larger ceramic bypass capacitor required between IN and GND |
| 4 | EN/EN | input | Logic input for power switch enable control; logic high level activates the switch |
| 5 | FLT | output | Low-level-active open-drain fault output; asserted when overcurrent or overheating conditions occur |
| 6 | OUT | power_out | Power switch output; supplies current to load |
| 7 | OUT | power_out | Power switch output; supplies current to load |
| 8 | OUT | power_out | Power switch output; supplies current to load |
| 9 | PowerPad | power_in | Exposed pad internally connected to GND; solder to ground plane or PCB ground layer to reduce thermal resistance and junction temperature |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | MSOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
## CAD (KiCad official)
- Symbol: `TPS2069CDGNR-2`
- Footprint: `Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.5x1.8mm`
- 3D model: MSOP-8-EP (KiCad packages3D, STEP)
- Annotated 3D hero: `tps2069cdgnr-2-hero.glb` (dashed pad outlines, silkscreen with pin 1, signal names; the [adom-hero standard](https://wiki.adom.inc/adom/component-hero)) is what the viewer shows. Downloads and EDA use the clean model, `tps2069cdgnr-2-etched.glb`.
- 3D model files: `tps2069cdgnr-2-etched.step` / `tps2069cdgnr-2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps2069cdgnr-2.step` / `tps2069cdgnr-2.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps2000c) (51 pp, sha256 `8d24f6ead5b760bb`, retrieved 2026-10-02, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps2069cdgnr-2-datasheet.pdf)