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Name	Last commit message	Last updated
docs	tps2051adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
viewers	tps2051adr: viewers · Ray	1mo ago
package.json	Publish 0.1.0 · Ray	1mo ago
page.json	tps2051adr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	1mo ago
README.md	tps2051adr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	1mo ago
tps2051adr-etched.fit.json	tps2051adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
tps2051adr-etched.glb	tps2051adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
tps2051adr-etched.step	tps2051adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
tps2051adr.glb	Publish 0.1.0 · Ray	1mo ago
tps2051adr.kicad_mod	Publish 0.1.0 · Ray	1mo ago
tps2051adr.kicad_sym	Publish 0.1.0 · Ray	1mo ago
tps2051adr.lbr	Publish 0.1.0 · Ray	1mo ago
tps2051adr.step	Publish 0.1.0 · Ray	1mo ago

TPS2051ADR

Texas Instruments · Power Distribution Switches · SOIC-8

TPS2051ADR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Device ground return for the switch and internal control circuitry. Tie to the system 0 V rail.
2	IN	power_in	Power-switch input voltage (2.7 V to 5.5 V). Pins 2 and 3 are the source of the internal N-channel high-side MOSFET and must be tied together and bypassed close to the device.
3	IN	power_in	Power-switch input voltage (2.7 V to 5.5 V). Pins 2 and 3 are the source of the internal N-channel high-side MOSFET and must be tied together and bypassed close to the device.
4	EN	input	Enable input, CMOS/TTL compatible. Logic HIGH turns the power switch on (TPS205xA is active-high). Do not leave floating.
5	OC	output	Overcurrent flag, open-drain active-low. Asserts low when the switch enters current limit or thermal shutdown. Requires an external pull-up resistor to a logic rail (typ. 10 kΩ to VCC).
6	OUT	power_out	Power-switch output (drain of the internal N-channel high-side MOSFET). Pins 6, 7 and 8 are the same OUT node and must be tied together; rated 500 mA continuous per channel, 0.9 A typical short-circuit current limit.
7	OUT	power_out	Power-switch output (drain of the internal N-channel high-side MOSFET). Pins 6, 7 and 8 are the same OUT node and must be tied together; rated 500 mA continuous per channel, 0.9 A typical short-circuit current limit.
8	OUT	power_out	Power-switch output (drain of the internal N-channel high-side MOSFET). Pins 6, 7 and 8 are the same OUT node and must be tied together; rated 500 mA continuous per channel, 0.9 A typical short-circuit current limit.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Power Management (PMIC)
Pins	8

Ordering variants

Same part, different packaging or reel option.

TPS2051ADRD
TPS2051ADR

CAD (KiCad official)

Symbol: TPS2051ADR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: tps2051adr-etched.step / tps2051adr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2051adr.step / tps2051adr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (None pp, sha256 e6c3c187a6b9b0bc, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF