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TPS2024IDRG4Q1

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Texas Instruments Power Distribution Switches, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS2024IDRG4Q1

Texas Instruments · Power Distribution Switches · SOIC-8

TPS2024IDRG4Q1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground connection for the device.
2 IN power_in Input voltage to the power switch, which operates from 2.7 V to 5.5 V.
3 IN power_in Input voltage to the power switch, which operates from 2.7 V to 5.5 V.
4 EN input Active-low logic enable that turns on the power switch when driven low and is compatible with TTL and CMOS logic levels.
5 OC output Open-drain overcurrent logic output that is asserted active-low during an overcurrent or overtemperature condition.
6 OUT power_out Power-switch output of the high-side N-channel MOSFET, which has a maximum on-state resistance of 50 mΩ at VI(IN) = 5 V.
7 OUT power_out Power-switch output of the high-side N-channel MOSFET, which has a maximum on-state resistance of 50 mΩ at VI(IN) = 5 V.
8 OUT power_out Power-switch output of the high-side N-channel MOSFET, which has a maximum on-state resistance of 50 mΩ at VI(IN) = 5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VI(IN) 2.7 5.5 V 4
Enable input voltage range VI(EN) 0 5.5 V 4
Continuous output current TPS2024 IO 0 2 A TPS2024 4
Operating virtual junction temperature range TJ -40 125 °C 4
Input voltage range (absolute maximum) VI(IN) -0.3 6 V with respect to GND 4
Output voltage range (absolute maximum) VO(OUT) -0.3 V max printed as VI(IN) + 0.3 V 4
Input voltage range EN (absolute maximum) VI(EN) -0.3 6 V 4
Operating virtual junction temperature range (absolute maximum) TJ -40 125 °C 4
Storage temperature range Tstg -65 150 °C 4
Human body model ESD protection 2 kV Human body model 4
Machine model ESD protection 200 V Machine model 4
Charged device model ESD protection 750 V Charged device model (CDM) 4
Total power dissipation, package D 725 mW TA ≤ 25°C; derating 5.8 mW/°C above TA = 25°C 4
Thermal resistance junction-to-ambient, SOIC RθJA 172 °C/W SOIC 19
Static drain-source on-state resistance rDS(on) 33 43.5 43.5 mΩ VI(IN) = 5 V, IO = 1.8 A, TJ = 25°C 5
Static drain-source on-state resistance rDS(on) 38 57.5 mΩ VI(IN) = 5 V, IO = 1.8 A, TJ = 85°C 5
Static drain-source on-state resistance rDS(on) 44 62.5 mΩ VI(IN) = 5 V, IO = 1.8 A, TJ = 125°C 5
Static drain-source on-state resistance rDS(on) 37 48.5 mΩ VI(IN) = 3.3 V, IO = 1.8 A, TJ = 25°C 5
Static drain-source on-state resistance rDS(on) 43 68.5 mΩ VI(IN) = 3.3 V, IO = 1.8 A, TJ = 85°C 5
Static drain-source on-state resistance rDS(on) 51 87 mΩ VI(IN) = 3.3 V, IO = 1.8 A, TJ = 125°C 5
Static drain-source on-state resistance rDS(on) 30 43.5 mΩ VI(IN) = 5 V, IO = 1 A, TJ = 25°C 5
Static drain-source on-state resistance rDS(on) 43 62.5 mΩ VI(IN) = 5 V, IO = 1 A, TJ = 125°C 5
Static drain-source on-state resistance rDS(on) 31 48.5 mΩ VI(IN) = 3.3 V, IO = 1 A, TJ = 25°C 5
Static drain-source on-state resistance rDS(on) 48 87 mΩ VI(IN) = 3.3 V, IO = 1 A, TJ = 125°C 5
High-level input voltage EN VIH 2 V 2.7 V ≤ VI(IN) ≤ 5.5 V, full range 5
Low-level input voltage EN VIL 0.8 V 4.5 V ≤ VI(IN) ≤ 5.5 V, full range 5
Low-level input voltage EN VIL 0.5 V 2.7 V ≤ VI(IN) ≤ 4.5 V, full range 5
Input current EN II -0.5 0.5 mA EN = 0 V or EN = VI(IN), full range 5
Turnon time ton 20 ms CL = 100 mF, RL = 10 Ω, full range 5
Turnoff time toff 40 ms CL = 100 mF, RL = 10 Ω, full range 5
Short-circuit output current TPS2024 IOS 2 3 4.2 A VI = 5.5 V, OUT connected to GND, device enabled into short circuit, 25°C 5
Supply current, low-level output 0.3 1 mA No load on OUT, EN = VI(IN), 25°C 6
Supply current, low-level output 10 mA No load on OUT, EN = VI(IN), full range 6
Supply current, high-level output 58 75 mA No load on OUT, EN = 0 V, 25°C 6
Supply current, high-level output 100 mA No load on OUT, EN = 0 V, full range 6
Leakage current 10 mA OUT connected to ground, EN = VI(IN), full range 6
Undervoltage lockout low-level input voltage 2 2.5 V full range 6
Undervoltage lockout hysteresis 100 mV 25°C 6
Overcurrent output low voltage VOL(OC) 0.4 V IO = 10 mA, full range 6
Overcurrent off-state current 1 mA VO = 5 V, VO = 3.3 V, full range; specified by design 6

CAD (KiCad official)

  • Symbol: TPS2024IDRG4Q1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tps2024idrg4q1-etched.step / tps2024idrg4q1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2024idrg4q1.step / tps2024idrg4q1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 96c12f53a3191566, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF