TPS2024DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground reference for the device.
2	IN	power_in	Input voltage to the power switch, with an operating range of 2.7 V to 5.5 V.
3	IN	power_in	Input voltage to the power switch, with an operating range of 2.7 V to 5.5 V.
4	EN	input	Enable input; logic-low turns on the power switch, and the input is compatible with both TTL and CMOS logic levels.
5	OC	output	Overcurrent logic output, active low, asserted during an overcurrent or overtemperature condition and open drain.
6	OUT	power_out	Power-switch output of the N-channel high-side MOSFET, which has a maximum on-state resistance of 50 mΩ at VI(IN) = 5 V.
7	OUT	power_out	Power-switch output of the N-channel high-side MOSFET, which has a maximum on-state resistance of 50 mΩ at VI(IN) = 5 V.
8	OUT	power_out	Power-switch output of the N-channel high-side MOSFET, which has a maximum on-state resistance of 50 mΩ at VI(IN) = 5 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage operating range	VI(IN)	2.7		5.5	V		4
Enable input voltage operating range	VI(EN)	0		5.5	V		4
Continuous output current	IO	0		2	A	TPS2024 variant	4
Operating virtual junction temperature range	TJ	-40		125	°C		4
Input voltage range (absolute)	VI(IN)	-0.3		6	V	with respect to GND	4
Output voltage range (absolute)	VO(OUT)	-0.3			V	maximum VI(IN) + 0.3 V, with respect to GND	4
Enable input voltage range (absolute)	VI(EN)	-0.3		6	V	with respect to GND	4
Operating virtual junction temperature range (absolute)	TJ	-40		125	°C		4
Storage temperature range	Tstg	-65		150	°C		4
Lead temperature soldering				260	°C	1,6 mm (1/16 inch) from case for 10 seconds	4
Electrostatic discharge human body model				2	kV	Human body model	4
Electrostatic discharge machine model				200	V	Machine model	4
Electrostatic discharge charged device model				750	V	Charged device model (CDM)	4
Continuous total power dissipation rating				725	mW	D package, TA ≤ 25°C	4
Static drain-source on-state resistance	rDS(on)		33	36	mΩ	VI(IN) = 5 V, TJ = 25°C, IO = 1.8 A	5
Static drain-source on-state resistance	rDS(on)		38	46	mΩ	VI(IN) = 5 V, TJ = 85°C, IO = 1.8 A	5
Static drain-source on-state resistance	rDS(on)		44	50	mΩ	VI(IN) = 5 V, TJ = 125°C, IO = 1.8 A	5
Static drain-source on-state resistance	rDS(on)		37	41	mΩ	VI(IN) = 3.3 V, TJ = 25°C, IO = 1.8 A	5
Static drain-source on-state resistance	rDS(on)		43	52	mΩ	VI(IN) = 3.3 V, TJ = 85°C, IO = 1.8 A	5
Static drain-source on-state resistance	rDS(on)		51	61	mΩ	VI(IN) = 3.3 V, TJ = 125°C, IO = 1.8 A	5
Static drain-source on-state resistance	rDS(on)		30	34	mΩ	VI(IN) = 5 V, TJ = 25°C, IO = 0.18 A	5
Static drain-source on-state resistance	rDS(on)		35	41	mΩ	VI(IN) = 5 V, TJ = 85°C, IO = 0.18 A	5
Static drain-source on-state resistance	rDS(on)		39	47	mΩ	VI(IN) = 5 V, TJ = 125°C, IO = 0.18 A	5
Static drain-source on-state resistance	rDS(on)		33	37	mΩ	VI(IN) = 3.3 V, TJ = 25°C, IO = 0.18 A	5
Static drain-source on-state resistance	rDS(on)		39	46	mΩ	VI(IN) = 3.3 V, TJ = 85°C, IO = 0.18 A	5
Static drain-source on-state resistance	rDS(on)		44	56	mΩ	VI(IN) = 3.3 V, TJ = 125°C, IO = 0.18 A	5
High-level input voltage	VIH	2			V	2.7 V ≤ VI(IN) ≤ 5.5 V	5
Low-level input voltage	VIL			0.8	V	4.5 V ≤ VI(IN) ≤ 5.5 V	5
Low-level input voltage	VIL			0.5	V	2.7 V ≤ VI(IN) ≤ 4.5 V	5
Input current	II	-0.5		0.5	μA	EN = 0 V or EN = VI(IN)	5
Supply current, low-level output			0.3	1	μA	TJ = 25°C, No load on OUT, EN = VI(IN)	5
Supply current, low-level output				10	μA	-40°C ≤ TJ ≤ 125°C, No load on OUT, EN = VI(IN)	5
Supply current, high-level output			58	75	μA	TJ = 25°C, No load on OUT, EN = 0 V	5
Supply current, high-level output			75	100	μA	-40°C ≤ TJ ≤ 125°C, No load on OUT, EN = 0 V	5
Leakage current				10	μA	OUT connected to ground, EN = VI(IN), -40°C ≤ TJ ≤ 125°C	5
Short-circuit output current	IOS	2.2	3	3.8	A	TJ = 25°C, VI = 5.5 V, OUT connected to GND, device enabled into short circuit	5
Low-level output voltage	VOL(OC)			0.4	V	IO = 10 mA	5
Off-state current				1	μA	VO = 5 V, VO = 3.3 V	5
Undervoltage lockout low-level input voltage			2	2.5	V		5
Undervoltage lockout hysteresis			100		mV	TJ = 25°C	5
Rise time, output	tr		6.1		ms	VI(IN) = 5.5 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω	5
Rise time, output	tr		8.6		ms	VI(IN) = 2.7 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω	5
Fall time, output	tf		3.4		ms	VI(IN) = 5.5 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω	5
Fall time, output	tf		3		ms	VI(IN) = 2.7 V, CL = 1 μF, TJ = 25°C, RL = 10 Ω	5
Turnon time	ton		20		ms	CL = 100 μF, RL = 10 Ω	5
Turnoff time	toff		40		ms	CL = 100 μF, RL = 10 Ω	5
Thermal resistance junction-to-ambient, SOIC	RθJA		172		°C/W	SOIC package	19

CAD (KiCad official)

Symbol: TPS2024DR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: tps2024dr-etched.step / tps2024dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2024dr.step / tps2024dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (30 pp, sha256 f42743bfcffed509, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS2024DR

Verified TPS2024DR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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