Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

TPS1HA08BQPWPRQ1

Texas Instruments · Global Sourcing Parts · HTSSOP-16-EP

TPS1HA08BQPWPRQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Device ground; in reverse battery the current flowing into GND must not exceed 50 mA (IGND absolute maximum, VBB < 0 V), so an external ground-protection network is recommended.
2 SNS output Analog sense output that carries a current proportional to the load current (IOUT/4600), the VBB voltage, or the device temperature as selected by SEL1 and SEL2, with an internal clamp at about 5.9 V; it also signals faults at ISNSFH, and the sense resistor should be terminated to the microcontroller ground.
3 LATCH input Selects fault handling: when low the switch automatically retries after a fault clears and tRETRY expires, and when high the switch stays latched off until LATCH is taken low; input thresholds are VIL 0.8 V and VIH 2 V, with an absolute range of -1 V to 7 V.
4 EN input Active-high switch enable with VIL 0.8 V and VIH 2 V thresholds, recommended range -1 V to 5.5 V, and an internal 1 MΩ pulldown; in the watchdog-enabled version E, EN must be pulsed periodically to keep the switch on.
5 ST output Open-drain, active-low status output that is pulled low on a fault (overtemperature, current limit, energy limit, open load or short to battery) and must be pulled up externally; VOL is at most 0.4 V at 1 mA, with an absolute range of -1 V to 7 V.
6 VOUT output Switched high-side output to the load; all six VOUT pins (6 to 11) must be shorted together on the PCB, and an internal VBB-to-VOUT clamp limits the voltage when inductive loads are switched off.
7 VOUT output Switched high-side output to the load; all six VOUT pins (6 to 11) must be shorted together on the PCB, and an internal VBB-to-VOUT clamp limits the voltage when inductive loads are switched off.
8 VOUT output Switched high-side output to the load; all six VOUT pins (6 to 11) must be shorted together on the PCB, and an internal VBB-to-VOUT clamp limits the voltage when inductive loads are switched off.
9 VOUT output Switched high-side output to the load; all six VOUT pins (6 to 11) must be shorted together on the PCB, and an internal VBB-to-VOUT clamp limits the voltage when inductive loads are switched off.
10 VOUT output Switched high-side output to the load; all six VOUT pins (6 to 11) must be shorted together on the PCB, and an internal VBB-to-VOUT clamp limits the voltage when inductive loads are switched off.
11 VOUT output Switched high-side output to the load; all six VOUT pins (6 to 11) must be shorted together on the PCB, and an internal VBB-to-VOUT clamp limits the voltage when inductive loads are switched off.
12 NC unconnected No internal connection; the datasheet lists this pin as not connected.
13 NC unconnected No internal connection; the datasheet lists this pin as not connected.
14 SEL1 input Diagnostic select 1 that chooses between VBB and junction-temperature sensing on SNS (with SEL2 selecting load current when both are low); input thresholds are VIL 0.8 V and VIH 2 V, with an internal 1 MΩ pulldown.
15 SEL2 input Diagnostic select 2 that works with SEL1 to choose the SNS signal and must be connected to module ground through RPROT to enable automatic turn-on during reverse battery; with SEL2 = 0 V, VBB measurement is unavailable, and input thresholds are VIL 0.8 V and VIH 2 V.
16 DIA_EN input Active-high diagnostic enable that activates analog sensing, open-load and short-to-battery detection when the switch is off; input thresholds are VIL 0.8 V and VIH 2 V, recommended range -1 V to 5.5 V, and an internal 1 MΩ pulldown.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-16-EP
Category Global Sourcing Parts
Pins 17

CAD (KiCad official)

  • Symbol: TPS1HA08BQPWPRQ1
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: tps1ha08bqpwprq1-etched.step / tps1ha08bqpwprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps1ha08bqpwprq1.step / tps1ha08bqpwprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (62 pp, sha256 a1d902aeb153f667, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF