TPS16850VMAR - 9 V to 80 V, 20 A eFuse

{
 "schema": "adom/verification@1",
 "part": "TPS16850VMAR",
 "variants": [
  {
   "mpn": "TPS16850VMAR",
   "note": "auto-retry variant, 73 A fixed fast trip; 2500-piece large tape and reel (SLVSHA1D p.3, p.50)",
   "stocked": false
  }
 ],
 "entries": [
  {
   "date": "2026-10-21",
   "by": {
    "name": "Claude (AI), automated checks, not yet reviewed by a person",
    "handle": "claude"
   },
   "status": "verified",
   "title": "Pinout matches the datasheet",
   "scope": [
    "symbol"
   ],
   "variants": [
    "*"
   ],
   "checks": [
    {
     "text": "Symbol pins match SLVSHA1D Table 5-1 (p.4-5): 1 ILIM, 2 IMON, 3 IREF, 4 dVdT, 5 GND, 6 SFT_SEL, 7-8 OUT, 9 VDD, 10/22/23 IN, 11/17/21 NC, 12 MODE, 13 FLT (active low), 14 ITIMER, 15 TEMP, 16 EN/UVLO, 18 OVP, 19 PGOOD, 20 SWEN, exposed pad (24) IN",
     "result": "pass"
    },
    {
     "text": "Electrical types: IN, VDD, GND power in; OUT power out; EN/UVLO, OVP, MODE input; FLT and PGOOD open drain; SWEN and TEMP bidirectional; resistor/capacitor set pins passive; NC no_connect",
     "result": "pass"
    },
    {
     "text": "Every pin sits on the 2.54 mm grid: yes (adom-symbol 1.2.6 put the first pin of each column at y = -2.00 with 8.35 mm group gaps; all 24 pins moved by provenance/tools/snap_symbol.py)",
     "result": "pass"
    },
    {
     "text": "Fusion .lbr: NC pins typed nc (adom-lbr 2.47.5 wrote io; fixed by provenance/tools/lbr_fix.py), every pin visible=both, lint PASS",
     "result": "pass"
    },
    {
     "text": "Altium SchLib read back with adom-lbr import-altium: 24 pins, names shown; NC pins read back as Passive because Altium has no no-connect pin type (use a No ERC marker on the sheet)",
     "result": "note"
    }
   ],
   "evidence": [
    {
     "label": "tps16850vmar-ds-p4.png",
     "href": "docs/figures/tps16850vmar-ds-p4.png"
    },
    {
     "label": "tps16850vmar-ds-p5.png",
     "href": "docs/figures/tps16850vmar-ds-p5.png"
    }
   ],
   "files": {
    "tps16850vmar.kicad_sym": "6744ba16ebb60b9fec757df856b244d3d4d36acceecd46d845679a4faa2fa7d7",
    "tps16850vmar.lbr": "9ace87d7b3714abc4ca70199f149594570fc1534f0ada5a85238ad61cdf31411",
    "altium/TPS16850VMAR.SchLib": "e550ad3980c965a9b69876a5da309df57b446e386df64a65149d2c8a50d47d5e"
   }
  },
  {
   "date": "2026-10-21",
   "by": {
    "name": "Claude (AI), automated checks, not yet reviewed by a person",
    "handle": "claude"
   },
   "status": "verified",
   "title": "Footprint equals TI's recommended land pattern",
   "scope": [
    "footprint"
   ],
   "variants": [
    "*"
   ],
   "checks": [
    {
     "text": "Overlay on SLVSHA1D p.55 at TI's printed 15X scale: 69.2 % of the copper outline on TI's strokes (TI draws the metal under mask of pads 7, 10, 22 dashed), comb mask openings 97.4 % on TI's green",
     "result": "pass"
    },
    {
     "text": "Pad by pad against TI's VMA0023A footprint published through Ultra Librarian: copper, mask and paste of all 24 pad numbers agree to 0.050 mm2 or less (corner treatment only); the 12 vias are at the same positions",
     "result": "pass"
    },
    {
     "text": "Pads 7, 10 and 22 are solder-mask defined combs over a larger copper rectangle, as TI draws them; pads 6 and 17 are L shapes; exposed pad paste is TI's six 0.98 x 1.04 mm windows (p.56, 76 % coverage)",
     "result": "pass"
    },
    {
     "text": "KiCad's standard library has no VMA0023A footprint, so no KiCad comparison is possible",
     "result": "note"
    },
    {
     "text": "adom-lbr 2.47.5 drops KiCad custom-pad shapes and paste-only pads: the Fusion and Altium libraries are made from provenance/tps16850vmar-lbr-input.kicad_mod, the same copper as rectangle unions, copper-only pads with mask and paste expansion -1.2 mm; Fusion gets TI's six paste windows on tCream by hand; Altium gets one exposed-pad paste aperture with the same area (expansion -0.174 mm) because adom-lbr writes no paste-layer regions",
     "result": "note"
    }
   ],
   "evidence": [
    {
     "label": "tps16850vmar-footprint-check.png",
     "href": "docs/proof/tps16850vmar-footprint-check.png"
    },
    {
     "label": "tps16850vmar-ds-p55.png",
     "href": "docs/figures/tps16850vmar-ds-p55.png"
    },
    {
     "label": "tps16850vmar-ds-p56.png",
     "href": "docs/figures/tps16850vmar-ds-p56.png"
    }
   ],
   "files": {
    "tps16850vmar.kicad_mod": "a4d037c209a248d09f6d1501b6df71442a5bb021a5022c6d159bd36c82693a0c",
    "tps16850vmar.lbr": "9ace87d7b3714abc4ca70199f149594570fc1534f0ada5a85238ad61cdf31411",
    "altium/TPS16850VMAR.PcbLib": "2b9263bf6f0d5a18fd6372f6d5317e820d9886dc1e2ced07cb520136232a0e0d"
   }
  },
  {
   "date": "2026-10-21",
   "by": {
    "name": "Claude (AI), automated checks, not yet reviewed by a person",
    "handle": "claude"
   },
   "status": "verified",
   "title": "Pin 1 orientation agrees across datasheet, footprint, 3D model and symbol",
   "scope": [
    "footprint",
    "3d",
    "symbol"
   ],
   "variants": [
    "*"
   ],
   "checks": [
    {
     "text": "Datasheet: pin 1 (ILIM) on the left side 0.5 mm above the centre line in the top view (Figure 5-1, p.4; land pattern p.55), pin-1 index corner and exposed-pad chamfer at the top left (p.54)",
     "result": "pass"
    },
    {
     "text": "Footprint: pad 1 at (-2.875, -0.5) in KiCad's Y-down frame, silkscreen dot to its left, fab outline chamfered at the top-left corner; numbering counter-clockwise (1-5 down the left, 6 corner, 7-10 along the bottom, 11-16 up the right, 17 corner, 18-21 along the top right to left, 22-23 top left)",
     "result": "pass"
    },
    {
     "text": "3D model: pin-1 terminal at (-2.75, +0.5) in the Y-up 3D frame (= pad 1), exposed-pad chamfer at the top-left corner; component-hero align check OK, offset 0.0 mm, zero rotation",
     "result": "pass"
    },
    {
     "text": "Symbol pin 1 = ILIM; Fusion and Altium map pin 1 to pad 1 (read back)",
     "result": "pass"
    },
    {
     "text": "Tape and reel: TI quadrant Q1 for pin 1 (p.52)",
     "result": "pass"
    }
   ],
   "evidence": [
    {
     "label": "tps16850vmar-pin1-check.png",
     "href": "docs/proof/tps16850vmar-pin1-check.png"
    },
    {
     "label": "tps16850vmar-ds-p4.png",
     "href": "docs/figures/tps16850vmar-ds-p4.png"
    },
    {
     "label": "tps16850vmar-ds-p52.png",
     "href": "docs/figures/tps16850vmar-ds-p52.png"
    }
   ],
   "files": {
    "tps16850vmar.kicad_mod": "a4d037c209a248d09f6d1501b6df71442a5bb021a5022c6d159bd36c82693a0c",
    "tps16850vmar.step": "34e33e779b6b92ffc048bf33a89dd3df7f246fd69638259933d5915d814a55f8",
    "tps16850vmar-etched.step": "15ef0f3945e0f6a08b63528edee6df68de23bae11e79c865b36fa0ffd3276ed1",
    "tps16850vmar.kicad_sym": "6744ba16ebb60b9fec757df856b244d3d4d36acceecd46d845679a4faa2fa7d7"
   }
  },
  {
   "date": "2026-10-21",
   "by": {
    "name": "Claude (AI), automated checks, not yet reviewed by a person",
    "handle": "claude"
   },
   "status": "verified",
   "title": "3D model inside TI's package drawing",
   "scope": [
    "3d"
   ],
   "variants": [
    "*"
   ],
   "checks": [
    {
     "text": "Bottom view over SLVSHA1D p.54: 97.3 % of the model's edge pixels on TI's strokes at a fitted 118.25 px/mm (TI 10X = 118.1 px/mm at 300 dpi)",
     "result": "pass"
    },
    {
     "text": "Side view: terminal exposures on TI's (0.2) marks; 70.1 % edge overlap; TI draws the body at A max 1.5 mm, the model is at the nominal 1.4 mm",
     "result": "pass"
    },
    {
     "text": "Every printed dimension at its nominal (table in provenance/3d-model.json)",
     "result": "pass"
    },
    {
     "text": "Virtual MPN etch gate PASS (axis, upright with pin 1 left, size, flat, group); labelled virtual: TI's real marking is TPS16850",
     "result": "pass"
    },
    {
     "text": "TI's manufacturer STEP was not reachable with plain HTTP (Ultra Librarian export behind reCAPTCHA); the model is AI-built from the drawing",
     "result": "note"
    }
   ],
   "evidence": [
    {
     "label": "tps16850vmar-model-vs-drawing-bottom.png",
     "href": "docs/proof/tps16850vmar-model-vs-drawing-bottom.png"
    },
    {
     "label": "tps16850vmar-model-vs-drawing-side.png",
     "href": "docs/proof/tps16850vmar-model-vs-drawing-side.png"
    },
    {
     "label": "tps16850vmar-etched.check.png",
     "href": "docs/proof/tps16850vmar-etched.check.png"
    },
    {
     "label": "tps16850vmar-ds-p54.png",
     "href": "docs/figures/tps16850vmar-ds-p54.png"
    }
   ],
   "files": {
    "tps16850vmar.step": "34e33e779b6b92ffc048bf33a89dd3df7f246fd69638259933d5915d814a55f8",
    "tps16850vmar-etched.step": "15ef0f3945e0f6a08b63528edee6df68de23bae11e79c865b36fa0ffd3276ed1",
    "tps16850vmar-hero.glb": "5835866ecf6e8e2a408cd69f0b0f1863f6decb13f396c27613b06ca05ab14aac"
   }
  },
  {
   "date": "2026-10-21",
   "by": {
    "name": "Claude (AI), automated checks, not yet reviewed by a person",
    "handle": "claude"
   },
   "status": "open",
   "title": "Still to do",
   "scope": [
    "*"
   ],
   "variants": [
    "*"
   ],
   "checks": [
    {
     "text": "Compare with TI's own STEP (Ultra Librarian) when someone can download it through a browser",
     "result": "open"
    },
    {
     "text": "Open the Fusion .lbr and Altium libraries in the native tools and look at the comb pads, paste windows and NC pins",
     "result": "open"
    },
    {
     "text": "A person reviews this page",
     "result": "open"
    }
   ],
   "evidence": [],
   "files": {}
  }
 ]
}