TPS16850VMAR - 9 V to 80 V, 20 A eFuse

{
 "schema": "adom/heatsink-via@1",
 "mpn": "TPS16850VMAR",
 "source": "TI SLVSHA1D p.55 LAND PATTERN EXAMPLE (VMA0023A): 12 vias, (0.2) TYP drill, at x -1.45 -0.59 0.59 1.45 and TI y +0.875 +0.075 -0.725 (KiCad y -0.875 -0.075 +0.725)",
 "ep": {
  "number": "24",
  "name": "IN",
  "w_mm": 3.4,
  "h_mm": 2.35,
  "x_mm": 0.0,
  "y_mm": -0.075,
  "frame": "KiCad footprint, y down"
 },
 "via": {
  "drill_mm": 0.2,
  "ring_mm": 0.15,
  "diameter_mm": 0.5,
  "pitch_mm": 0.8,
  "tented": true,
  "count": 12,
  "positions": [
   [
    -1.45,
    -0.875
   ],
   [
    -0.59,
    -0.875
   ],
   [
    0.59,
    -0.875
   ],
   [
    1.45,
    -0.875
   ],
   [
    -1.45,
    -0.075
   ],
   [
    -0.59,
    -0.075
   ],
   [
    0.59,
    -0.075
   ],
   [
    1.45,
    -0.075
   ],
   [
    -1.45,
    0.725
   ],
   [
    -0.59,
    0.725
   ],
   [
    0.59,
    0.725
   ],
   [
    1.45,
    0.725
   ]
  ],
  "pitch_note": "rows 0.8 mm apart; columns at TI's positions (0.86 / 1.18 / 0.86 mm), not a uniform grid"
 },
 "note": "TI's positions and drill are used instead of the Adom default 0.3 mm drill, 0.8 mm grid. The pad is electrically IN (the FET input), so these vias carry current and heat into the input plane. The 0.5 mm via pad (0.15 mm ring) is Adom's choice; TI prints only the drill.",
 "hero_glb": {
  "layer": "vias",
  "node": "Adom.HeatsinkVias",
  "board_mm": 1.6,
  "alpha": 0.35
 },
 "footprint": "tps16850vmar.kicad_mod: plated thru_hole pads numbered 24, layers *.Cu (tented), property pad_prop_heatsink",
 "lanes": {
  "fusion": "<pad name=\"[email protected]\" drill=\"0.2\" diameter=\"0.5\"> joined to pin IN@4",
  "altium": "multi-layer plated pads named 24 with 0.2 mm holes"
 }
}