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TPS16630PWPT

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Texas Instruments Surge Protection Devices (SPDs), HTSSOP-20. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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TPS16630PWPT

Texas Instruments · Surge Protection Devices (SPDs) · HTSSOP-20

TPS16630PWPT from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Power input connected to the drain of the internal FET; connect IN and P_IN together and keep the IN pins from being left unconnected.
2 IN power_in Power input connected to the drain of the internal FET; connect IN and P_IN together and keep the IN pins from being left unconnected.
3 IN power_in Power input connected to the drain of the internal FET; the datasheet table gives no name for this pin, so IN is inferred from the shared IN description and must be confirmed against Figure 5-2.
4 N.C unconnected No internal connection.
5 N.C unconnected No internal connection.
6 P_IN power_in Device supply voltage; always connect P_IN directly to IN, with a 4.5 V to 60 V operating input range (V(IN) = V(P_IN)).
7 UVLO input Input for setting the programmable undervoltage lockout threshold; an undervoltage event turns off the internal FET and asserts FLT, and UVLO must not be left floating.
8 OVP input Input for setting the adjustable overvoltage protection threshold (TPS16630 only); an overvoltage event turns off the internal FET and asserts FLT.
9 GND power_in Connect GND to the system ground.
10 dVdT bidirectional A capacitor between this pin and GND sets the output voltage slew rate; leaving the pin open powers up the device in thermal regulation mode for fast output charging.
11 ILIM bidirectional A resistor from this pin to GND sets the overload current limit (R(ILIM) 3 kΩ to 30 kΩ).
12 MODE input Mode-select pin for the overload fault response: open selects latch-off and shorted to GND selects auto-retry.
13 SHDN input Shutdown pin; pulling SHDN low puts the device into a low-quiescent-current shutdown, and cycling SHDN resets a device latched off by a fault.
14 IMON output Analog current monitor output that provides a scaled-down current of the internal FET; a resistor to GND converts it to a voltage, and the pin should be left floating if unused.
15 FLT output Open-drain fault indicator output; leave it floating or connect it to GND if used.
16 PGOOD output Active-high open-drain power-good output that goes high when the internal FET is enhanced and goes low during a fault or when SHDN is pulled low; connect to GND or leave floating if unused.
17 N.C unconnected No internal connection.
18 OUT power_out Power output of the device.
19 OUT power_out Power output of the device.
20 N.C unconnected No internal connection.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20
Category Circuit Protection
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating input voltage V(IN), V(P_IN) 4.5 60 V 8
Supply current, enabled IQ(ON) 1.38 1.7 mA V(SHDN) = 2V 8
Supply current, shutdown IQ(OFF) 21 60 µA V(SHDN) = 0V 8
UVLO threshold, rising V(UVLOR) 1.176 1.2 1.224 V 8
UVLO threshold, falling V(UVLOF) 1.09 1.122 1.15 V 8
UVLO input leakage current I(UVLO) -150 8 150 nA 0V ≤ V(UVLO) ≤ 60V 8
OVP threshold, rising V(OVPR) 1.176 1.2 1.224 V 8
OVP threshold, falling V(OVPF) 1.09 1.122 1.15 V 8
OVP input leakage current I(OVP) -150 0 150 nA 0V ≤ V(OVP) ≤ 4V 8
Overload current limit I(OL) 0.54 0.6 0.66 A R(ILIM) = 30kΩ, V(IN), V(OUT) = 1V 8
Overload current limit I(OL) 1.84 2 2.16 A R(ILIM) = 9kΩ, V(IN), V(OUT) = 1V 8
Overload current limit I(OL) 4.185 4.5 4.815 A R(ILIM) = 4.02kΩ, V(IN), V(OUT) = 1V 8
Overload current limit I(OL) 5.58 6 6.42 A R(ILIM) = 3kΩ, V(IN), V(OUT) = 1V 8
On-resistance IN to OUT, TJ = 25°C RON 26 30.44 34.5 mΩ 0.6A ≤ I(OUT) ≤ 6A, TJ = 25°C 9
On-resistance IN to OUT, TJ = 85°C RON 33 45 mΩ 0.6A ≤ I(OUT) ≤ 6A, TJ = 85°C 9
On-resistance IN to OUT, -40 to +125°C RON 19 30.44 53 mΩ 0.6A ≤ I(OUT) ≤ 6A, -40°C ≤ TJ ≤ +125°C 9
dVdT charge current I(dVdT) 1.775 2 2.225 µA V(dVdT) = 0V 9
dVdT to OUT gain GAIN(dVdT) 23.5 25 26 V/V 9
dVdT maximum capacitor voltage V(dVdTmax) 3.8 4.17 4.75 V 9
dVdT discharge resistance R(dVdT) 10 16.6 26.6 Ω 9
IMON current gain GAIN(IMON) 25.66 27.9 30.14 µA/A 0.6A ≤ I(OUT) < 2A 9
IMON current gain GAIN(IMON) 26.22 27.9 29.58 µA/A 2A ≤ I(OUT) ≤ 6A 9
SHDN open-circuit voltage V(SHDN) 2.48 2.7 3.3 V I(SHDN) = 0.1µA 9
FLT pull-down resistance R(FLT) 36 70 130 Ω 9
FLT input leakage current I(FLT) -150 6 150 nA 0V ≤ V(FLT) ≤ 60V 9
PGOOD pull-down resistance R(PGOOD) 36 70 130 Ω 9
PGOOD input leakage current I(PGOOD) -150 6 150 nA 0V ≤ V(PGOOD) ≤ 60V 9
Thermal regulation setpoint T(J_REG) 136 145 154 ºC 9
UVLO switch turn-off delay UVLO_toff(dly) 9 11 16 µs UVLO falls 20mV below V(UVLOF), causing FLT to fall 10
UVLO to FLT deassert delay tUVLO_FLT(dly) 500 617 700 µs UVLO rises, causing FLT to rise 10
OVP switch turn-off delay OVP_toff(dly) 8.5 11 14 µs OVP rises 20mV above V(OVPR), causing FLT to fall 10
Shutdown entry delay tSD(dly) 0.8 1 1.5 µs SHDN falls below V(SHUTF), causing FET to turn off 10
Soft short response time tFASTTRIP(dly) 2.2 3.2 4.5 µs I(FASTTRIP) < I(OUT) < I(SCP) 10
Current limit maximum duration tCL_PLIM(dly) 129 162 202 ms 10
Current limit FLT delay tCL_PLIM_FLT(dly) 1.09 1.3 1.6 ms 10
Fast-charge output ramp time t(FASTCHARGE) 350 495 700 µs C(dVdT) open, 10% to 90% V(OUT), C(OUT) = 1µF, V(IN) = 24V 10
PGOOD deglitch delay, rising edge tPGOODR 8 11.5 13 ms Rising edge 10
PGOOD deglitch delay, falling edge tPGOODF 8 10 13 ms Falling edge 10
TSD retry delay t(TSD_retry) 500 648 800 ms MODE = GND 10
Thermal regulation timeout t(Treg_timeout) 1.1 1.25 1.5 s 10
Input voltage, IN and P_IN V(IN), V(P_IN) 4.5 60 V 7
Input voltage, OUT, UVLO, PGOOD, FLT V(OUT), V(UVLO), V(PGOOD), V(FLT) 0 60 V 7
Input voltage, OVP, dVdT, IMON, MODE V(OVP), V(dVdT), V(IMON), V(MODE) 0 4 V 7
Input voltage, SHDN V(SHDN) 0 5 V 7
Current-limit programming resistance R(ILIM) 3 30 kΩ 7
Operating junction temperature TJ -40 25 125 °C 7
Input voltage, IN, P_IN, OUT, UVLO, FLT, PGOOD V(IN), V(P_IN), V(OUT), V(UVLO), V(FLT), V(PGOOD) -0.3 67 V 7
Input voltage, IN and P_IN (10 ms transient) V(IN), V(P_IN) -0.3 75 V 10 ms transient, TA = 25°C 7
Input voltage, OVP, dVdT, IMON, MODE, SHDN, ILIM V(OVP), V(dVdT), V(IMON), V(MODE), V(SHDN), V(ILIM) -0.3 5.5 V 7
Sink current, FLT, dVdT, PGOOD IFLT, IdVdT, IPGOOD 10 mA 7
Operating junction temperature TJ -40 150 °C 7
Transient junction temperature TJ -65 °C Upper limit printed as T(TSD) 7
Storage temperature Tstg -65 150 °C 7
Junction-to-ambient thermal resistance RθJA 32.2 °C/W PWP (HTSSOP-20) package 8
Junction-to-case (top) thermal resistance RθJC(top) 23.4 °C/W PWP (HTSSOP-20) package 8
Junction-to-board thermal resistance RθJB 10 °C/W PWP (HTSSOP-20) package 8
Junction-to-top characterization parameter ΨJT 0.3 °C/W PWP (HTSSOP-20) package 8
Junction-to-board characterization parameter ΨJB 9.9 °C/W PWP (HTSSOP-20) package 8
Junction-to-case (bottom) thermal resistance RθJC(bot) 3.6 °C/W PWP (HTSSOP-20) package 8

CAD (KiCad official)

  • Symbol: TPS16630PWPT
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps16630pwpt-etched.step / tps16630pwpt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps16630pwpt.step / tps16630pwpt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 ef1077e8989a204c, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF