# TPS1100PWR

**Texas Instruments** · MOSFETs · TSSOP-8

TPS1100PWR from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SOURCE | passive | Source terminal of the P-channel MOSFET; per Note A, all source pins must be connected together in every application. |
| 2 | SOURCE | passive | Source terminal of the P-channel MOSFET; per Note A, all source pins must be connected together in every application. |
| 3 | SOURCE | passive | Source terminal of the P-channel MOSFET; per Note A, all source pins must be connected together in every application. |
| 4 | GATE | input | Gate input with TTL- and CMOS-compatible levels; VGS(th) is -1.5 V maximum, and the absolute maximum gate-to-source rating is printed as '2 or -15 V' in the extracted text. |
| 5 | DRAIN | passive | Drain terminal of the P-channel MOSFET; per Note A, all drain pins must be connected together, and the drain-to-source voltage is rated -15 V. |
| 6 | DRAIN | passive | Drain terminal of the P-channel MOSFET; per Note A, all drain pins must be connected together, and the drain-to-source voltage is rated -15 V. |
| 7 | DRAIN | passive | Drain terminal of the P-channel MOSFET; per Note A, all drain pins must be connected together, and the drain-to-source voltage is rated -15 V. |
| 8 | DRAIN | passive | Drain terminal of the P-channel MOSFET; per Note A, all drain pins must be connected together, and the drain-to-source voltage is rated -15 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate-to-source threshold voltage | VGS(th) | -1 | -1.25 | -1.5 | V | VDS = VGS, ID = –250 µA | 4 |
| Reverse gate current, drain short circuited to source | IGSS | -100 |  | 100 | nA | VDS = 0 V, VGS = –12 V | 4 |
| Zero-gate-voltage drain current (TJ = 25°C) | IDSS |  |  | -0.5 | µA | VDS = –12 V, VGS = 0 V, TJ = 25°C | 4 |
| Zero-gate-voltage drain current (TJ = 125°C) | IDSS |  |  | -10 | µA | VDS = –12 V, VGS = 0 V, TJ = 125°C | 4 |
| Static drain-to-source on-state resistance | rDS(on) |  | 291 | 400 | mΩ | VGS = –4.5 V, ID = –0.5 A | 4 |
| Static drain-to-source on-state resistance | rDS(on) |  | 476 | 700 | mΩ | VGS = –3 V, ID = 02A (as printed) | 4 |
| Static drain-to-source on-state resistance | rDS(on) |  | 606 | 850 | mΩ | VGS = –2.7 V, ID = –0.2 A | 4 |
| Drain-to-source voltage | VDS |  |  | -15 | V |  | 3 |
| Gate-to-source voltage | VGS | -15 |  | 2 | V |  | 3 |
| Continuous drain current (TJ = 150°C), PW package | ID | -0.4 |  | 0.4 | A | PW package, TA = 25°C, VGS = –2.7 V | 3 |
| Continuous drain current (TJ = 150°C), PW package | ID | -0.23 |  | 0.23 | A | PW package, TA = 125°C, VGS = –2.7 V | 3 |
| Continuous drain current (TJ = 150°C), PW package | ID | -0.53 |  | 0.53 | A | PW package, TA = 25°C, VGS = –3 V | 3 |
| Continuous drain current (TJ = 150°C), PW package | ID | -0.27 |  | 0.27 | A | PW package, TA = 125°C, VGS = –3 V | 3 |
| Continuous drain current (TJ = 150°C), PW package | ID | -0.81 |  | 0.81 | A | PW package, TA = 25°C, VGS = –4.5 V | 3 |
| Continuous drain current (TJ = 150°C), PW package | ID | -0.37 |  | 0.37 | A | PW package, TA = 125°C, VGS = –4.5 V | 3 |
| Continuous drain current (TJ = 150°C), PW package | ID | -1.27 |  | 1.27 | A | PW package, TA = 25°C, VGS = –10 V | 3 |
| Continuous drain current (TJ = 150°C), PW package | ID | -0.58 |  | 0.58 | A | PW package, TA = 125°C, VGS = –10 V | 3 |
| Pulsed drain current | ID | -7 |  | 7 | A | TA = 25°C | 3 |
| Continuous source current (diode conduction) | IS |  |  | -1 | A | TA = 25°C | 3 |
| Storage temperature range | Tstg | -55 |  | 150 | °C |  | 3 |
| Operating junction temperature range | TJ | -40 |  | 150 | °C |  | 3 |
| Operating free-air temperature range | TA | -40 |  | 125 | °C |  | 3 |
| Lead temperature |  |  |  | 260 | °C | 1/16 inch from case for 10 seconds | 3 |
| Power rating, PW package |  |  |  | 504 | mW | PW package, TA ≤ 25°C | 3 |
| Junction-to-ambient thermal resistance, PW package | RθJA |  | 248 |  | °C/W | PW package, FR4 board, no special thermal considerations | 3 |

## CAD (KiCad official)

- Symbol: `TPS1100PWR`
- Footprint: `Package_SO:TSSOP-8_3x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `tps1100pwr-etched.step` / `tps1100pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps1100pwr.step` / `tps1100pwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps1100.pdf) (15 pp, sha256 `936ccff12fa04953`, retrieved 2026-10-11, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps1100pwr-datasheet.pdf)