component
TPNXV75UPR
Public Made by Adomby adom
TECH PUBLIC MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
TPNXV75UPR
TECH PUBLIC · MOSFETs · SOT-23
TPNXV75UPR from TECH PUBLIC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate; gate-source voltage limit is ±8 V and threshold VGS(th) is -0.45 V min to -1 V max at ID=-250µA. |
| 2 | S | passive | Source of the P-channel MOSFET; drain-source voltage rating is -20 V and continuous drain current is -2.8 A. |
| 3 | D | passive | Drain of the P-channel MOSFET; VDS is -20 V max, continuous ID is -2.8 A and pulsed IDM is -10 A. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
CAD (KiCad official)
- Symbol:
TPNXV75UPR - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
tpnxv75upr-etched.step/tpnxv75upr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpnxv75upr.step/tpnxv75upr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TECH PUBLIC datasheet (4 pp, sha256
e622078ff4103294, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPNXV75UPR
**TECH PUBLIC** · MOSFETs · SOT-23
TPNXV75UPR from TECH PUBLIC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate; gate-source voltage limit is ±8 V and threshold VGS(th) is -0.45 V min to -1 V max at ID=-250µA. |
| 2 | S | passive | Source of the P-channel MOSFET; drain-source voltage rating is -20 V and continuous drain current is -2.8 A. |
| 3 | D | passive | Drain of the P-channel MOSFET; VDS is -20 V max, continuous ID is -2.8 A and pulsed IDM is -10 A. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
## CAD (KiCad official)
- Symbol: `TPNXV75UPR`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `tpnxv75upr-etched.step` / `tpnxv75upr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpnxv75upr.step` / `tpnxv75upr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603383968507588608) (4 pp, sha256 `e622078ff4103294`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tpnxv75upr-datasheet.pdf)