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TPNUP4114UCW1T2G
Public Made by Adomby adom
TECH PUBLIC ESD And Surge Protection (TVS/ESD), SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPNUP4114UCW1T2G
TECH PUBLIC · ESD And Surge Protection (TVS/ESD) · SOT-363
TPNUP4114UCW1T2G from TECH PUBLIC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CH1 | passive | ESD-protected high-speed I/O channel 1, steered by diodes to VP and VN, with 1.5pF typical channel capacitance and ±18kV air / ±14kV contact IEC 61000-4-2 protection. |
| 2 | VN | power_in | Negative supply/ground reference pin (GND) of the TVS array, with reverse stand-off of 5V max measured from pin 5 to pin 2. |
| 3 | CH2 | passive | ESD-protected high-speed I/O channel 2, steered by diodes to VP and VN, with 1.5pF typical channel capacitance and ±18kV air / ±14kV contact IEC 61000-4-2 protection. |
| 4 | CH4 | passive | ESD-protected high-speed I/O channel 4, steered by diodes to VP and VN, with 1.5pF typical channel capacitance and ±18kV air / ±14kV contact IEC 61000-4-2 protection. |
| 5 | VP | power_in | Positive supply (VDD) pin of the TVS array, with operating supply voltage (VDD-GND) of 6V max and 5V reverse stand-off voltage. |
| 6 | CH3 | passive | ESD-protected high-speed I/O channel 3, steered by diodes to VP and VN, with 1.5pF typical channel capacitance and ±18kV air / ±14kV contact IEC 61000-4-2 protection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-363 |
| Category | Circuit Protection |
| Pins | 6 |
CAD (KiCad official)
- Symbol:
TPNUP4114UCW1T2G - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files:
tpnup4114ucw1t2g-etched.step/tpnup4114ucw1t2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpnup4114ucw1t2g.step/tpnup4114ucw1t2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TECH PUBLIC datasheet (4 pp, sha256
5b77c98b5385f2c2, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPNUP4114UCW1T2G
**TECH PUBLIC** · ESD And Surge Protection (TVS/ESD) · SOT-363
TPNUP4114UCW1T2G from TECH PUBLIC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CH1 | passive | ESD-protected high-speed I/O channel 1, steered by diodes to VP and VN, with 1.5pF typical channel capacitance and ±18kV air / ±14kV contact IEC 61000-4-2 protection. |
| 2 | VN | power_in | Negative supply/ground reference pin (GND) of the TVS array, with reverse stand-off of 5V max measured from pin 5 to pin 2. |
| 3 | CH2 | passive | ESD-protected high-speed I/O channel 2, steered by diodes to VP and VN, with 1.5pF typical channel capacitance and ±18kV air / ±14kV contact IEC 61000-4-2 protection. |
| 4 | CH4 | passive | ESD-protected high-speed I/O channel 4, steered by diodes to VP and VN, with 1.5pF typical channel capacitance and ±18kV air / ±14kV contact IEC 61000-4-2 protection. |
| 5 | VP | power_in | Positive supply (VDD) pin of the TVS array, with operating supply voltage (VDD-GND) of 6V max and 5V reverse stand-off voltage. |
| 6 | CH3 | passive | ESD-protected high-speed I/O channel 3, steered by diodes to VP and VN, with 1.5pF typical channel capacitance and ±18kV air / ±14kV contact IEC 61000-4-2 protection. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-363 |
| Category | Circuit Protection |
| Pins | 6 |
## CAD (KiCad official)
- Symbol: `TPNUP4114UCW1T2G`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files: `tpnup4114ucw1t2g-etched.step` / `tpnup4114ucw1t2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpnup4114ucw1t2g.step` / `tpnup4114ucw1t2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588913699381370881) (4 pp, sha256 `5b77c98b5385f2c2`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tpnup4114ucw1t2g-datasheet.pdf)