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TPNUP4102XV6T1G
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TECH PUBLIC ESD And Surge Protection (TVS/ESD), SOT563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPNUP4102XV6T1G
TECH PUBLIC · ESD And Surge Protection (TVS/ESD) · SOT563
TPNUP4102XV6T1G from TECH PUBLIC, in a SOT563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | Bi-directional TVS channel line (pin 1) clamped to the common pins 2 and 5, with 12V reverse working voltage and 25V max clamping at 3A (8/20µs). |
| 2 | GND | power_in | Common return of the TVS array, tied internally to pin 5 and connected to ground. |
| 3 | I/O2 | passive | Bi-directional TVS channel line (pin 3) clamped to the common pins 2 and 5, with 12V reverse working voltage and 25V max clamping at 3A (8/20µs). |
| 4 | I/O3 | passive | Bi-directional TVS channel line (pin 4) clamped to the common pins 2 and 5, with 12V reverse working voltage and 25V max clamping at 3A (8/20µs). |
| 5 | GND | power_in | Common return of the TVS array, tied internally to pin 2 and connected to ground. |
| 6 | I/O4 | passive | Bi-directional TVS channel line (pin 6) clamped to the common pins 2 and 5, with 12V reverse working voltage and 25V max clamping at 3A (8/20µs). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT563 |
| Category | Circuit Protection |
| Pins | 6 |
CAD (KiCad official)
- Symbol:
TPNUP4102XV6T1G - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT563 (KiCad packages3D, STEP)
- 3D model files:
tpnup4102xv6t1g-etched.step/tpnup4102xv6t1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpnup4102xv6t1g.step/tpnup4102xv6t1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TECH PUBLIC datasheet (4 pp, sha256
fc96416a349ff8e0, retrieved 2026-10-14, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPNUP4102XV6T1G
**TECH PUBLIC** · ESD And Surge Protection (TVS/ESD) · SOT563
TPNUP4102XV6T1G from TECH PUBLIC, in a SOT563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | Bi-directional TVS channel line (pin 1) clamped to the common pins 2 and 5, with 12V reverse working voltage and 25V max clamping at 3A (8/20µs). |
| 2 | GND | power_in | Common return of the TVS array, tied internally to pin 5 and connected to ground. |
| 3 | I/O2 | passive | Bi-directional TVS channel line (pin 3) clamped to the common pins 2 and 5, with 12V reverse working voltage and 25V max clamping at 3A (8/20µs). |
| 4 | I/O3 | passive | Bi-directional TVS channel line (pin 4) clamped to the common pins 2 and 5, with 12V reverse working voltage and 25V max clamping at 3A (8/20µs). |
| 5 | GND | power_in | Common return of the TVS array, tied internally to pin 2 and connected to ground. |
| 6 | I/O4 | passive | Bi-directional TVS channel line (pin 6) clamped to the common pins 2 and 5, with 12V reverse working voltage and 25V max clamping at 3A (8/20µs). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT563 |
| Category | Circuit Protection |
| Pins | 6 |
## CAD (KiCad official)
- Symbol: `TPNUP4102XV6T1G`
- Footprint: `Package_TO_SOT_SMD:SOT-563`
- 3D model: SOT563 (KiCad packages3D, STEP)
- 3D model files: `tpnup4102xv6t1g-etched.step` / `tpnup4102xv6t1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpnup4102xv6t1g.step` / `tpnup4102xv6t1g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603003658065747968) (4 pp, sha256 `fc96416a349ff8e0`, retrieved 2026-10-14, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tpnup4102xv6t1g-datasheet.pdf)