component
TPNTGD1100LT1G
Public Made by Adomby adom
TECH PUBLIC Power Distribution Switches, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPNTGD1100LT1G
TECH PUBLIC · Power Distribution Switches · SOT-23-6
TPNTGD1100LT1G from TECH PUBLIC, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of Q1 (level-shift N-channel), shown as R2 in the circuit diagram, where an optional 0 to 100kΩ slew-rate control resistor connects to ground. |
| 2 | D2 | passive | Drain of Q2 (load switch output, VOUT), tied internally to pin 3 and carrying up to ±3.5 A continuous load current. |
| 3 | D2 | passive | Drain of Q2 (load switch output, VOUT), tied internally to pin 2 and carrying up to ±3.5 A continuous load current. |
| 4 | S2 | power_in | Source of Q2 (load switch input, VIN), rated 1.8 V to 8 V input with an 8 V absolute maximum. |
| 5 | G1 | input | ON/OFF gate input of Q1 with 1.5 V to 8 V logic level control, 8 V absolute maximum and 2000 V HBM ESD protection. |
| 6 | D1/G2 | passive | Common drain of Q1 and gate of Q2 (R1, C1 node), where an optional pull-up resistor R1 (typically 10kΩ to 1MΩ) and slew-rate capacitor C1 (typically 1000pF) connect. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
CAD (KiCad official)
- Symbol:
TPNTGD1100LT1G - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
tpntgd1100lt1g-etched.step/tpntgd1100lt1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpntgd1100lt1g.step/tpntgd1100lt1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TECH PUBLIC datasheet (6 pp, sha256
c99ba3d5c2898e7b, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPNTGD1100LT1G
**TECH PUBLIC** · Power Distribution Switches · SOT-23-6
TPNTGD1100LT1G from TECH PUBLIC, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of Q1 (level-shift N-channel), shown as R2 in the circuit diagram, where an optional 0 to 100kΩ slew-rate control resistor connects to ground. |
| 2 | D2 | passive | Drain of Q2 (load switch output, VOUT), tied internally to pin 3 and carrying up to ±3.5 A continuous load current. |
| 3 | D2 | passive | Drain of Q2 (load switch output, VOUT), tied internally to pin 2 and carrying up to ±3.5 A continuous load current. |
| 4 | S2 | power_in | Source of Q2 (load switch input, VIN), rated 1.8 V to 8 V input with an 8 V absolute maximum. |
| 5 | G1 | input | ON/OFF gate input of Q1 with 1.5 V to 8 V logic level control, 8 V absolute maximum and 2000 V HBM ESD protection. |
| 6 | D1/G2 | passive | Common drain of Q1 and gate of Q2 (R1, C1 node), where an optional pull-up resistor R1 (typically 10kΩ to 1MΩ) and slew-rate capacitor C1 (typically 1000pF) connect. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
## CAD (KiCad official)
- Symbol: `TPNTGD1100LT1G`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `tpntgd1100lt1g-etched.step` / `tpntgd1100lt1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpntgd1100lt1g.step` / `tpntgd1100lt1g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603149699369357312) (6 pp, sha256 `c99ba3d5c2898e7b`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tpntgd1100lt1g-datasheet.pdf)