main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 11d ago
viewers tpm60nb7s8-5: viewers · Ray 11d ago
package.json Publish 0.1.0 · Ray 11d ago
page.json Set visibility: public · Ray 11d ago
README.md Publish 0.1.0 · Ray 11d ago
tpm60nb7s8-5-etched.glb Publish 0.1.0 · Ray 11d ago
tpm60nb7s8-5-etched.step tpm60nb7s8-5: factory component page (tier=lcsc) · Ray 11d ago
tpm60nb7s8-5-hero.glb tpm60nb7s8-5: hero GLB from the etched model (keeps the MPN mark) · Ray 11d ago
tpm60nb7s8-5-hero.overlay.json Publish 0.1.0 · Ray 11d ago
tpm60nb7s8-5.glb Publish 0.1.0 · Ray 11d ago
tpm60nb7s8-5.kicad_mod Publish 0.1.0 · Ray 11d ago
tpm60nb7s8-5.kicad_sym Publish 0.1.0 · Ray 11d ago
tpm60nb7s8-5.lbr Publish 0.1.0 · Ray 11d ago
tpm60nb7s8-5.step Publish 0.1.0 · Ray 11d ago

TPM60NB7S8-5

TECH PUBLIC · MOSFETs · SOP-8

TPM60NB7S8-5 from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of MOSFET 1 (N-channel), with VDS rated to 60 V and continuous ID of 6 A.
2 G1 input Gate of MOSFET 1, with VGS rated to ±20 V and a gate threshold of 1.2 V min to 2.5 V max.
3 S2 passive Source of MOSFET 2 (N-channel), with VDS rated to 60 V and continuous ID of 6 A.
4 G2 input Gate of MOSFET 2, with VGS rated to ±20 V and a gate threshold of 1.2 V min to 2.5 V max.
5 D2 passive Drain of MOSFET 2, connected with pin 6, with VDS rated to 60 V and pulsed drain current up to 24 A.
6 D2 passive Drain of MOSFET 2, connected with pin 5, with VDS rated to 60 V and pulsed drain current up to 24 A.
7 D1 passive Drain of MOSFET 1, connected with pin 8, with VDS rated to 60 V and pulsed drain current up to 24 A.
8 D1 passive Drain of MOSFET 1, connected with pin 7, with VDS rated to 60 V and pulsed drain current up to 24 A.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: TPM60NB7S8-5
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tpm60nb7s8-5-etched.step / tpm60nb7s8-5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpm60nb7s8-5.step / tpm60nb7s8-5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (5 pp, sha256 68824f9b09655b94, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF