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TPM30NP67S8-4

TECH PUBLIC · MOSFETs · SOP-8

TPM30NP67S8-4 from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of the P-channel MOSFET (MOSFET 1, VDS = -30V, ID = -7A).
2 G1 input Gate of the P-channel MOSFET (MOSFET 1), VGS rated ±20V.
3 S2 passive Source of the N-channel MOSFET (MOSFET 2, VDS = 30V, ID = 6.5A).
4 G2 input Gate of the N-channel MOSFET (MOSFET 2), VGS rated ±20V.
5 D2 passive Drain of the N-channel MOSFET (MOSFET 2), shorted internally to pin 6; VDS = 30V.
6 D2 passive Drain of the N-channel MOSFET (MOSFET 2), shorted internally to pin 5; VDS = 30V.
7 D1 passive Drain of the P-channel MOSFET (MOSFET 1), shorted internally to pin 8; VDS = -30V.
8 D1 passive Drain of the P-channel MOSFET (MOSFET 1), shorted internally to pin 7; VDS = -30V.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: TPM30NP67S8-4
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tpm30np67s8-4-etched.step / tpm30np67s8-4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpm30np67s8-4.step / tpm30np67s8-4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (9 pp, sha256 04193c9aa075c8cc, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF