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TPM3067NPS8-1

Public Made by Adom

by adom

TECH PUBLIC MOSFETs, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs tpm3067nps8-1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers tpm3067nps8-1: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json tpm3067nps8-1: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md tpm3067nps8-1: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago
tpm3067nps8-1-etched.fit.json tpm3067nps8-1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tpm3067nps8-1-etched.glb tpm3067nps8-1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tpm3067nps8-1-etched.step tpm3067nps8-1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tpm3067nps8-1.glb Publish 0.1.0 · Ray 1mo ago
tpm3067nps8-1.kicad_mod Publish 0.1.0 · Ray 1mo ago
tpm3067nps8-1.kicad_sym Publish 0.1.0 · Ray 1mo ago
tpm3067nps8-1.lbr Publish 0.1.0 · Ray 1mo ago
tpm3067nps8-1.step Publish 0.1.0 · Ray 1mo ago

TPM3067NPS8-1

TECH PUBLIC · MOSFETs · SOP-8

TPM3067NPS8-1 from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of the N-channel MOSFET (Q1). Reference terminal for VGS1 measurement and body-diode anode of the N-CH device.
2 G1 input Gate of the N-channel MOSFET (Q1). VGS(th) typ 1.67 V, absolute max VGS = ±20 V. Drive to ≥4.5 V for full enhancement (RDS(on) ≤ 28 mΩ @ VGS=4.5V, ≤ 22 mΩ @ VGS=10V).
3 S2 passive Source of the P-channel MOSFET (Q2). Reference terminal for VGS2 measurement and body-diode cathode of the P-CH device.
4 G2 input Gate of the P-channel MOSFET (Q2). VGS(th) typ -1.53 V, absolute max VGS = ±20 V. Drive to ≤ -4.5 V for full enhancement (RDS(on) ≤ 45 mΩ @ VGS=-4.5V, ≤ 30 mΩ @ VGS=-10V).
5 D2 passive Drain of the P-channel MOSFET (Q2). Pins 5 and 6 are internally fused to D2 to share thermal/current load. BVDSS = -30 V, ID = -6 A continuous @ TA=25°C.
6 D2 passive Drain of the P-channel MOSFET (Q2), fused with pin 5. Shared for current handling and heat dissipation.
7 D1 passive Drain of the N-channel MOSFET (Q1), fused with pin 8. Shared for current handling and heat dissipation.
8 D1 passive Drain of the N-channel MOSFET (Q1). Pins 7 and 8 are internally fused to D1. BVDSS = 30 V, ID = 7 A continuous @ TA=25°C.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOP-8
Category Transistors/Thyristors
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • TPM3067NPS8-1

CAD (KiCad official)

  • Symbol: TPM3067NPS8-1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tpm3067nps8-1-etched.step / tpm3067nps8-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpm3067nps8-1.step / tpm3067nps8-1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (None pp, sha256 ec85d9861ff29787, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF