component

TPM3012PS8-5

Public Made by Adom

by adom

TECH PUBLIC MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorstpm3012ps8-5factory-2.0.0extractor-text
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 4h ago
viewers tpm3012ps8-5: viewers · Ray 4h ago
package.json Publish 0.1.0 · Ray 4h ago
page.json Set visibility: public · Ray 4h ago
README.md Publish 0.1.0 · Ray 4h ago
tpm3012ps8-5-etched.glb Publish 0.1.0 · Ray 4h ago
tpm3012ps8-5-etched.step tpm3012ps8-5: factory component page (tier=lcsc) · Ray 4h ago
tpm3012ps8-5-hero.glb tpm3012ps8-5: hero GLB from the etched model (keeps the MPN mark) · Ray 4h ago
tpm3012ps8-5-hero.overlay.json Publish 0.1.0 · Ray 4h ago
tpm3012ps8-5.glb Publish 0.1.0 · Ray 4h ago
tpm3012ps8-5.kicad_mod Publish 0.1.0 · Ray 4h ago
tpm3012ps8-5.kicad_sym Publish 0.1.0 · Ray 4h ago
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tpm3012ps8-5.step Publish 0.1.0 · Ray 4h ago

TPM3012PS8-5

TECH PUBLIC · MOSFETs · SOP-8

TPM3012PS8-5 from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source of the P-channel MOSFET, tied to pins 2 and 3; drain-source voltage limit is -30 V.
2 S passive Source of the P-channel MOSFET, tied to pins 1 and 3 in the same device.
3 S passive Source of the P-channel MOSFET, tied to pins 1 and 2 in the same device.
4 G input Gate of the P-channel MOSFET; gate-source voltage limit is ±20 V with threshold of -1 V min to -3 V max.
5 D passive Drain of the P-channel MOSFET, tied to pins 6, 7 and 8; continuous drain current is -12 A.
6 D passive Drain of the P-channel MOSFET, tied to pins 5, 7 and 8 in the same device.
7 D passive Drain of the P-channel MOSFET, tied to pins 5, 6 and 8 in the same device.
8 D passive Drain of the P-channel MOSFET, tied to pins 5, 6 and 7 in the same device.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: TPM3012PS8-5
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tpm3012ps8-5-etched.step / tpm3012ps8-5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpm3012ps8-5.step / tpm3012ps8-5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (6 pp, sha256 7f001c0c2414a7ce, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF