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TPM27524-SO1R

Public Made by Adom

by adom

3PEAK Gate Drivers, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

TPM27524-SO1R

3PEAK · Gate Drivers · SOP-8

TPM27524-SO1R from 3PEAK, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ENA input Channel A enable input; the enable high threshold is 1.7-2.3 V and the enable low threshold is 1.0-1.4 V, and it supports NC connection through internal pull-up resistors.
2 INA input Non-inverting logic input for channel A on the TPM27524, with TTL/CMOS thresholds and capability to withstand DC −5 V.
3 GND power_in Device ground.
4 INB input Non-inverting logic input for channel B on the TPM27524, with TTL/CMOS thresholds and capability to withstand DC −5 V.
5 OUTB output Channel B gate driver output, capable of 5-A peak source and sink current.
6 VDD power_in Power supply input; recommended operating range is 4.5 V to 23 V, with an absolute maximum of 25 V.
7 OUTA output Channel A gate driver output, capable of 5-A peak source and sink current.
8 ENB input Channel B enable input; the enable high threshold is 1.7-2.3 V and the enable low threshold is 1.0-1.4 V, and it supports NC connection through internal pull-up resistors.

Key specifications

Parameter Value
Manufacturer 3PEAK
Package SOP-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Start-up Current, based on TPM27524 Circuitry IDD(off) 40 100 μA VDD = 3.4 V, INA = H, INB = H 7
Supply under Voltage Lock Out Rising Threshold VON 3.91 4.2 4.5 V TJ = 25 °C 7
Supply under Voltage Lock Out Rising Threshold VON 3.7 4.2 4.65 V TJ = −40 °C, 150 °C 7
Supply under Voltage Lock Out Falling Threshold VOFF 3.4 3.9 4.4 V TJ = −40 °C, 150 °C 7
Supply under Voltage Lock Out Hysteresis VDD_H 0.2 0.3 0.5 V 7
Enable High Threshold VEN_H 1.7 1.9 2.3 V Enable high threshold 7
Enable Low Threshold VEN_L 1 1.2 1.4 V Enable low threshold 7
Enable Hysteresis VEN_HYS 0.52 0.7 0.88 V 7
Input Signal High Threshold VIN_H 1.65 1.95 2.3 V Input high threshold 7
Input Signal Low Threshold VIN_L 1 1.25 1.4 V Input low threshold 7
Input Hysteresis VIN_HYS 0.52 0.7 0.88 V 7
Output Peak Current IOUT -5 5 A CLOAD = 0.22 μF, FSW = 1 kHz 7
Output High Voltage VDD, VOH 40 mV IOUT = −10 mA 7
Output Low Voltage VOL 10 mV IOUT = 10 mA 7
Output Pull-up Resistance, PMOS ROH 1 1.6 3 Ω Pull-up only; IOUT = −10 mA 7
Output Pull-down Resistance ROL 0.15 0.5 1 Ω IOUT = 10 mA 7
Output Rise-time tR 7 18 ns CLOAD = 1.8 nF 7
Output Fall-time tF 6 10 ns CLOAD = 1.8 nF 7
Delay Matching between OUTA and OUTB tM 1 4 ns INA = INB, OUTA and OUTB measured at 50% 7
Minimal Pulse Width tPW 15 25 ns 7
Input to Output Propagation Delay tD1 6 14 23 ns CLOAD = 1.8 nF, 5-V INx pulse 7
Enable to Output Propagation Delay tD3 6 14 23 ns CLOAD = 1.8 nF, 5-V ENx pulse 7
Power Supply Voltage, VDD (recommended) VDD 4.5 23 V 5
Input Voltage Range INA, INB, INA+, INA-, INB+, INB-, ENA, ENB (recommended) 0 20 V 5
Operating Ambient Temperature Range -40 125 °C 5
Power Supply Voltage, VDD (absolute maximum) VDD -0.3 25 V 5
Output Voltage Range OUTA, OUTB -0.3 V 5
Output Voltage Range OUTA, OUTB (200-ns pulse) -2 V 200-ns pulse 5
Input Voltage Range INA, INB, INA+, INA-, INB+, INB-, ENA, ENB (absolute maximum) -5 20 V 5
Continuous Output Channel Current OUTA, OUTB -300 300 mA 5
Pulsed Output Channel Current OUTA, OUTB -5 5 A 500 ns 5
Operating Junction Temperature Range -40 150 °C 5
Storage Temperature Range TSTG -65 150 °C 5
Lead Temperature (Soldering) TL 260 °C Soldering, 10 sec 5
ESD Human Body Model HBM -6 6 kV ANSI/ESDA/JEDEC JS-001 5
ESD Charged Device Model CDM -1.5 1.5 kV ANSI/ESDA/JEDEC JS-002 5
Thermal Resistance Junction-to-Ambient, SOP8 θJA 122.3 °C/W SOP8 package 5
Thermal Resistance Junction-to-Case, SOP8 θJC 60.4 °C/W SOP8 package 5

CAD (KiCad official)

  • Symbol: TPM27524-SO1R
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tpm27524-so1r-etched.step / tpm27524-so1r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpm27524-so1r.step / tpm27524-so1r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 3PEAK datasheet (22 pp, sha256 4f9c58a13fa1b01e, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF