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TPM20V7NBLS8-2

TECH PUBLIC · MOSFETs · SOP-8

TPM20V7NBLS8-2 from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of MOSFET 1 (N-channel, VDS 20 V, ID 6 A at TC = 25°C).
2 G1 input Gate of MOSFET 1 (VGS ±12 V max, threshold VGS(TH) min 0.6 V at ID = 250 µA).
3 S2 passive Source of MOSFET 2 (N-channel, VDS 20 V, ID 6 A at TC = 25°C).
4 G2 input Gate of MOSFET 2 (VGS ±12 V max, threshold VGS(TH) min 0.6 V at ID = 250 µA).
5 D2 passive Drain of MOSFET 2 (VDS 20 V max, pulsed IDM 30 A, RDS(on) max 30 mΩ at VGS = 4.5 V).
6 D2 passive Drain of MOSFET 2 (VDS 20 V max, pulsed IDM 30 A, RDS(on) max 30 mΩ at VGS = 4.5 V).
7 D1 passive Drain of MOSFET 1 (VDS 20 V max, pulsed IDM 30 A, RDS(on) max 30 mΩ at VGS = 4.5 V).
8 D1 passive Drain of MOSFET 1 (VDS 20 V max, pulsed IDM 30 A, RDS(on) max 30 mΩ at VGS = 4.5 V).

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: TPM20V7NBLS8-2
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tpm20v7nbls8-2-etched.step / tpm20v7nbls8-2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpm20v7nbls8-2.step / tpm20v7nbls8-2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (5 pp, sha256 ccb1810d92c66efa, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF