component
TPL903245-S5TR
Public Made by Adomby adom
3PEAK Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPL903245-S5TR
3PEAK · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPL903245-S5TR from 3PEAK, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | Input voltage pin; bypass IN to GND with a 1 μF or greater capacitor, with IN operating from 1.75 V to 5.5 V. |
| 2 | GND | power_in | Ground reference pin; connect the GND pin directly to the PCB ground plane. |
| 3 | EN | input | Active-high regulator enable; drive above VIH(EN) of 1.2 V to turn the regulator on and below VIL(EN) of 0.4 V to turn it off, or connect EN directly to IN for automatic startup. |
| 4 | NC | unconnected | No connection. |
| 5 | OUT | output | Regulated output voltage pin; bypass OUT to GND with a 1 μF or greater capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 3PEAK |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IN, EN voltage (absolute maximum) | -0.3 | 6 | V | 6 | |||
| OUT voltage (absolute maximum) | -0.3 | 6 | V | 6 | |||
| Junction temperature range (absolute maximum) | TJ | -40 | 150 | °C | 6 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 6 | ||
| Lead temperature (soldering) | TL | 260 | °C | Soldering 10 sec | 6 | ||
| HBM ESD protection | HBM | -6000 | 6000 | V | ANSI/ESDA/JEDEC JS-001 | 6 | |
| CDM ESD protection | CDM | -1500 | 1500 | V | ANSI/ESDA/JEDEC JS-002 | 6 | |
| IN input voltage (recommended) | VIN | 1.75 | 5.5 | V | 6 | ||
| EN voltage (recommended) | VEN | 0 | V | 6 | |||
| OUT voltage (recommended) | VOUT | 0 | 5.5 | V | 6 | ||
| Output capacitor COUT | COUT | 1 | 10 | µF | 6 | ||
| ESR of COUT | ESR | 0.001 | 0.1 | Ω | 6 | ||
| Junction temperature range (recommended) | TJ | -40 | 125 | °C | 6 | ||
| Power dissipation | PD | 0 | 400 | mW | 6 | ||
| Output voltage accuracy | VOUT | -2 | 2 | % | −40°C ≤ TJ ≤ +125°C, 0 mA ≤ IOUT ≤ 300 mA | 7 | |
| Input supply voltage range | VIN | 1.75 | 5.5 | V | 7 | ||
| Ground pin current | IGND | 120 | µA | IOUT = 0 mA | 7 | ||
| Shutdown current | ISHDN | 0.02 | 2 | µA | EN = GND | 7 | |
| EN logic-input high level | VIH(EN) | 1.2 | V | Output Enable | 7 | ||
| EN logic-input low level | VIL(EN) | 0 | 0.4 | V | Output Disable | 7 | |
| EN pin leakage current | IEN | 1 | 2 | µA | VEN = 5 V | 7 | |
| Line regulation | ΔVOUT | 1 | mV | VIN = VOUT(NOM) + 1 V to 5.5 V | 7 | ||
| Load regulation | ΔVOUT | 5 | mV | VIN = VOUT(NOM) + 1 V, IOUT = 1 mA to 300 mA | 7 | ||
| Dropout voltage | VDO | 28 | mV | VOUT = 3.3 V, IOUT = 100 mA | 7 | ||
| Dropout voltage | VDO | 80 | 180 | mV | VOUT = 3.3 V, IOUT = 300 mA | 7 | |
| Output current | IOUT | 0 | 300 | mA | VOUT in regulation | 7 | |
| Output current limit | ICL | 500 | 800 | mA | VOUT = 0.9 × VOUT(NOM) | 7 | |
| Short-circuit current limit | ISC | 100 | mA | RLOAD = 20 mΩ, TA = 25°C | 7 | ||
| Active output discharge resistance | RDIS | 290 | Ω | VEN < VIL(EN) | 7 | ||
| Power supply rejection ratio | PSRR | 82.1 | dB | IOUT = 20 mA, f = 100 Hz | 7 | ||
| Power supply rejection ratio | PSRR | 81.9 | dB | IOUT = 20 mA, f = 1 kHz | 7 | ||
| Power supply rejection ratio | PSRR | 87.9 | dB | IOUT = 20 mA, f = 10 kHz | 7 | ||
| Power supply rejection ratio | PSRR | 61.4 | dB | IOUT = 20 mA, f = 100 kHz | 7 | ||
| Power supply rejection ratio | PSRR | 44.7 | dB | IOUT = 20 mA, f = 1 MHz | 7 | ||
| Output noise voltage | VN | 8.6 | μVRMS | IOUT = 150 mA, BW = 10 Hz to 100 kHz | 7 | ||
| Start-up time | tSTR | 750 | μs | VOUT reaches 95% of nominal output voltage after EN = high | 7 | ||
| Thermal shutdown temperature | TSD | 165 | ºC | 7 | |||
| Thermal shutdown hysteresis | 15 | ºC | 7 | ||||
| Junction-to-ambient thermal resistance, SOT23-5 | θJA | 280 | °C/W | 6 | |||
| Junction-to-case thermal resistance, SOT23-5 | θJC | 62 | °C/W | 6 | |||
| Nominal output voltage (this MPN, 4.5 V option) | VOUT | 4.5 | V | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitor connection, the IN pin, and the GND pin of the system must be as small as possible. • It is recommended to use wide and thick copper to minimize I×R drop and heat dissipation. | 13 |
CAD (KiCad official)
- Symbol:
TPL903245-S5TR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tpl903245-s5tr-etched.step/tpl903245-s5tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpl903245-s5tr.step/tpl903245-s5tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 3PEAK datasheet (22 pp, sha256
5717499ceb17ed20, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPL903245-S5TR
**3PEAK** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPL903245-S5TR from 3PEAK, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | Input voltage pin; bypass IN to GND with a 1 μF or greater capacitor, with IN operating from 1.75 V to 5.5 V. |
| 2 | GND | power_in | Ground reference pin; connect the GND pin directly to the PCB ground plane. |
| 3 | EN | input | Active-high regulator enable; drive above VIH(EN) of 1.2 V to turn the regulator on and below VIL(EN) of 0.4 V to turn it off, or connect EN directly to IN for automatic startup. |
| 4 | NC | unconnected | No connection. |
| 5 | OUT | output | Regulated output voltage pin; bypass OUT to GND with a 1 μF or greater capacitor. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 3PEAK |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IN, EN voltage (absolute maximum) | | -0.3 | | 6 | V | | 6 |
| OUT voltage (absolute maximum) | | -0.3 | | 6 | V | | 6 |
| Junction temperature range (absolute maximum) | TJ | -40 | | 150 | °C | | 6 |
| Storage temperature range | TSTG | -65 | | 150 | °C | | 6 |
| Lead temperature (soldering) | TL | | | 260 | °C | Soldering 10 sec | 6 |
| HBM ESD protection | HBM | -6000 | | 6000 | V | ANSI/ESDA/JEDEC JS-001 | 6 |
| CDM ESD protection | CDM | -1500 | | 1500 | V | ANSI/ESDA/JEDEC JS-002 | 6 |
| IN input voltage (recommended) | VIN | 1.75 | | 5.5 | V | | 6 |
| EN voltage (recommended) | VEN | 0 | | | V | | 6 |
| OUT voltage (recommended) | VOUT | 0 | | 5.5 | V | | 6 |
| Output capacitor COUT | COUT | 1 | | 10 | µF | | 6 |
| ESR of COUT | ESR | 0.001 | | 0.1 | Ω | | 6 |
| Junction temperature range (recommended) | TJ | -40 | | 125 | °C | | 6 |
| Power dissipation | PD | 0 | | 400 | mW | | 6 |
| Output voltage accuracy | VOUT | -2 | | 2 | % | −40°C ≤ TJ ≤ +125°C, 0 mA ≤ IOUT ≤ 300 mA | 7 |
| Input supply voltage range | VIN | 1.75 | | 5.5 | V | | 7 |
| Ground pin current | IGND | | | 120 | µA | IOUT = 0 mA | 7 |
| Shutdown current | ISHDN | | 0.02 | 2 | µA | EN = GND | 7 |
| EN logic-input high level | VIH(EN) | 1.2 | | | V | Output Enable | 7 |
| EN logic-input low level | VIL(EN) | 0 | | 0.4 | V | Output Disable | 7 |
| EN pin leakage current | IEN | | 1 | 2 | µA | VEN = 5 V | 7 |
| Line regulation | ΔVOUT | | | 1 | mV | VIN = VOUT(NOM) + 1 V to 5.5 V | 7 |
| Load regulation | ΔVOUT | | | 5 | mV | VIN = VOUT(NOM) + 1 V, IOUT = 1 mA to 300 mA | 7 |
| Dropout voltage | VDO | | | 28 | mV | VOUT = 3.3 V, IOUT = 100 mA | 7 |
| Dropout voltage | VDO | | 80 | 180 | mV | VOUT = 3.3 V, IOUT = 300 mA | 7 |
| Output current | IOUT | 0 | | 300 | mA | VOUT in regulation | 7 |
| Output current limit | ICL | 500 | | 800 | mA | VOUT = 0.9 × VOUT(NOM) | 7 |
| Short-circuit current limit | ISC | | 100 | | mA | RLOAD = 20 mΩ, TA = 25°C | 7 |
| Active output discharge resistance | RDIS | | | 290 | Ω | VEN < VIL(EN) | 7 |
| Power supply rejection ratio | PSRR | | 82.1 | | dB | IOUT = 20 mA, f = 100 Hz | 7 |
| Power supply rejection ratio | PSRR | | 81.9 | | dB | IOUT = 20 mA, f = 1 kHz | 7 |
| Power supply rejection ratio | PSRR | | 87.9 | | dB | IOUT = 20 mA, f = 10 kHz | 7 |
| Power supply rejection ratio | PSRR | | 61.4 | | dB | IOUT = 20 mA, f = 100 kHz | 7 |
| Power supply rejection ratio | PSRR | | 44.7 | | dB | IOUT = 20 mA, f = 1 MHz | 7 |
| Output noise voltage | VN | | 8.6 | | μVRMS | IOUT = 150 mA, BW = 10 Hz to 100 kHz | 7 |
| Start-up time | tSTR | | 750 | | μs | VOUT reaches 95% of nominal output voltage after EN = high | 7 |
| Thermal shutdown temperature | TSD | | 165 | | ºC | | 7 |
| Thermal shutdown hysteresis | | | 15 | | ºC | | 7 |
| Junction-to-ambient thermal resistance, SOT23-5 | θJA | | 280 | | °C/W | | 6 |
| Junction-to-case thermal resistance, SOT23-5 | θJC | | 62 | | °C/W | | 6 |
| Nominal output voltage (this MPN, 4.5 V option) | VOUT | | 4.5 | | V | | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | capacitor connection, the IN pin, and the GND pin of the system must be as small as possible. • It is recommended to use wide and thick copper to minimize I×R drop and heat dissipation. | 13 |
## CAD (KiCad official)
- Symbol: `TPL903245-S5TR`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tpl903245-s5tr-etched.step` / `tpl903245-s5tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpl903245-s5tr.step` / `tpl903245-s5tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [3PEAK datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8757055082577694720) (22 pp, sha256 `5717499ceb17ed20`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tpl903245-s5tr-datasheet.pdf)