TPL820F33-89TR
Public Made by Adomby adom
3PEAK Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-89-3. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
TPL820F33-89TR
3PEAK · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-89-3
TPL820F33-89TR from 3PEAK, in a SOT-89-3. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage pin. Fixed 3.3 V nominal (±1% at TJ = 25°C), sourcing up to 180 mA. Requires a 2.2 µF to 22 µF low-ESR ceramic output capacitor for stability. |
| 2 | GND | power_in | Ground reference pin. Connect directly to the PCB ground plane for best thermal performance and noise immunity. |
| 3 | IN | power_in | Input voltage pin. Accepts 3.6 V to 42 V (absolute max 45 V). Requires a bypass capacitor to GND; typical application uses a ceramic input capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 3PEAK |
| Package | SOT-89-3 |
| Category | PMIC |
| Pins | 3 |
Ordering variants
Same part, different packaging or reel option.
TPL820F33-89TRTPL820F33-89TRF28-89TRTPL820F33-89TRF30-89TRTPL820F33-89TRF50-89TRTPL820F33-5TRTPL820F33-89TRF28-5TRTPL820F33-89TRF30-5TRTPL820F33-89TRF50-5TRTPL820F33-89TRU33-5TRTPL820F33-89TRU28-5TRTPL820F33-89TRU30-5TRTPL820F33-89TRU50-5TRTPL820F33-3TRTPL820F33-89TRF28-3TRTPL820F33-89TRF30-3TRTPL820F33-89TRF50-3TRTPL820F33-ST4RTPL820F33-89TRF28-ST4RTPL820F33-89TRF30-ST4RTPL820F33-89TRF50-ST4R
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum Input Voltage | VIN | -0.3 | 45 | V | 6 | ||
| Maximum Output Voltage | VOUT | -0.3 | 6 | V | 6 | ||
| Maximum Operating Power Dissipation | PD | 1.5 | W | 6 | |||
| Junction Temperature Range | TJ | -40 | 150 | °C | 6 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 6 | ||
| Lead Temperature (Soldering 10 sec) | TL | 260 | °C | 10 sec soldering | 6 | ||
| HBM Human Body Model ESD | HBM | -2.5 | 2.5 | kV | ANSI/ESDA/JEDEC JS-001 | 6 | |
| CDM Charged Device Model ESD | CDM | -2 | 2 | kV | ANSI/ESDA/JEDEC JS-002 | 6 | |
| Input Voltage (recommended) | VIN | 3.6 | 42 | V | 6 | ||
| Output Voltage (recommended) | VOUT | 1.2 | 5 | V | 6 | ||
| Output Current | IOUT | 0 | 180 | mA | 6 | ||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | 6 | ||
| Power Dissipation (SOT89-3 Package) | PD | 0 | 1000 | mW | SOT89-3 package | 6 | |
| Input voltage range | VIN | 3.6 | 42 | V | 7 | ||
| Quiescent current | IQ | 2 | 5 | µA | IOUT = 0 mA | 7 | |
| Quiescent current | IQ | 390 | µA | IOUT = 180 mA | 7 | ||
| Output voltage accuracy | VOUT | -1 | 1 | % | TJ = +25°C | 7 | |
| Output voltage accuracy | VOUT | -2 | 2 | % | −40°C ≤ TJ ≤ +125°C | 7 | |
| Line regulation | ΔVOUT | 3 | mV | VIN = VOUT(NOM) + 1 V to 42 V, or VIN ≥ 3.6 V, IOUT = 1 mA | 7 | ||
| Load regulation | ΔVOUT | 20 | mV | IOUT = 1 mA to 180 mA | 7 | ||
| Dropout voltage | VDO | 200 | 600 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 50 mA | 7 | |
| Dropout voltage | VDO | 720 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 180 mA | 7 | ||
| Output current | IOUT | 0 | 180 | mA | VOUT in regulation | 7 | |
| Output current limit | ICL | 180 | 800 | mA | VOUT = 0.9 × VOUT(NOM) | 7 | |
| Power supply rejection ratio | PSRR | 75 | dB | IOUT = 10 mA, f = 100 Hz, COUT = 4.7 µF | 7 | ||
| Power supply rejection ratio | PSRR | 65 | dB | IOUT = 10 mA, f = 1 kHz, COUT = 4.7 µF | 7 | ||
| Output noise voltage | VN | 110 | µVRMS | IOUT = 10 mA, BW = 10 Hz to 100 kHz | 7 | ||
| Output noise voltage | VN | 70 | µVRMS | IOUT = 10 mA, BW = 100 Hz to 100 kHz | 7 | ||
| VIN under-voltage lock-out | UVLO | 2.9 | V | VIN rising | 7 | ||
| Thermal shutdown threshold | TSD | 160 | ºC | 7 | |||
| Thermal shutdown hysteresis | 40 | ºC | 7 | ||||
| Thermal resistance junction-to-ambient (SOT89-3) | θJA | 63 | °C/W | SOT89-3 package | 6 | ||
| Thermal resistance junction-to-case (SOT89-3) | θJC | 9.41 | °C/W | SOT89-3 package | 6 |
CAD (KiCad official)
- Symbol:
TPL820F33-89TR - Footprint:
Package_TO_SOT_SMD:SOT-89-3 - 3D model: SOT-89-3 (KiCad packages3D, STEP)
- 3D model files:
tpl820f33-89tr-etched.step/tpl820f33-89tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpl820f33-89tr.step/tpl820f33-89tr.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tpl820f33-89tr.step |
57 KB | You want the bare part, or you mark your own boards. |
tpl820f33-89tr-etched.step |
2.1 MB | You want the part with TPL820F33-89TR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 531 faces against 42 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 3PEAK datasheet (19 pp, sha256
9a939658365898a8, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).