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TPL810F33-5TR

Public Made by Adom

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3PEAK Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tpl810f33-5trfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TPL810F33-5TR

3PEAK · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPL810F33-5TR from 3PEAK, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage pin; the datasheet recommends VIN of 3.6 V to 24 V, with an absolute maximum of 45 V, and a 2.2 µF or greater input capacitor with a 0.1 µF bypass in parallel.
2 GND power_in Ground reference pin that must be connected directly to the PCB ground plane.
3 NC unconnected No connection.
4 NC unconnected No connection on the fixed-output version (TPL810F33-5TR); this pin is the FB feedback input only on the adjustable (TPL810ADJ-5TR) version.
5 OUT power_out Regulated output voltage pin, 3.3 V for this fixed-output part, with a 2.2 µF to 22 µF low-ESR ceramic output capacitor required for stability.

Key specifications

Parameter Value
Manufacturer 3PEAK
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 3.6 24 V 7
Quiescent current IQ 2 5 µA IOUT = 0 mA 7
Quiescent current IQ 400 µA IOUT = 180 mA; single printed value, column placement not explicit 7
VIN under-voltage lock-out UVLO 2.9 3.6 V VIN rising; two printed values, column placement not explicit 7
Output voltage accuracy VOUT -1 1 % TJ = +25°C 7
Output voltage accuracy VOUT -2 2 % −40°C ≤ TJ ≤ +125°C 7
Line regulation ΔVOUT 3 mV VIN = VOUT(NOM) + 1 V to 24 V, or VIN ≥ 3.6 V, IOUT = 1 mA; single printed value, column placement not explicit 7
Load regulation ΔVOUT 20 mV IOUT = 1 mA to 180 mA; single printed value, column placement not explicit 7
Dropout voltage VDO 200 600 mV VIN = 0.98 × VOUT(NOM), IOUT = 50 mA 7
Dropout voltage VDO 800 mV VIN = 0.98 × VOUT(NOM), IOUT = 180 mA; single printed value, column placement not explicit 7
Output current IOUT 0 180 mA VOUT in regulation 7
Output current limit ICL 180 800 mA VOUT = 0.9 × VOUT(NOM) 7
Power supply rejection ratio PSRR 75 dB IOUT = 10 mA, f = 100 Hz, COUT = 4.7 µF; single printed value, column placement not explicit 7
Power supply rejection ratio PSRR 65 dB IOUT = 10 mA, f = 1 kHz, COUT = 4.7 µF; single printed value, column placement not explicit 7
Output noise voltage VN 110 µVRMS IOUT = 10 mA, BW = 10 Hz to 100 kHz; single printed value, column placement not explicit 7
Output noise voltage VN 70 µVRMS IOUT = 10 mA, BW = 100 Hz to 100 kHz; single printed value, column placement not explicit 7
Thermal shutdown threshold TSD 160 ºC single printed value, column placement not explicit 7
Thermal shutdown hysteresis 40 ºC single printed value, column placement not explicit 7
VIN input voltage VIN -0.3 45 V with respect to GND 6
VOUT output voltage (fixed version) VOUT -0.3 6 V Fixed version 6
Junction temperature range TJ -40 150 °C 6
Storage temperature range TSTG -65 150 °C 6
Lead temperature (soldering 10 sec) TL 260 °C Soldering 10 sec 6
HBM ESD HBM -2.5 2.5 kV ANSI/ESDA/JEDEC JS-001 6
CDM ESD CDM -2 2 kV ANSI/ESDA/JEDEC JS-002 6
VIN input voltage VIN 3.6 24 V 6
VOUT output voltage (fixed version) VOUT 1.2 5 V Fixed version 6
Output current IOUT 0 180 mA 6
Operating junction temperature range TJ -40 125 °C 6
Power dissipation (SOT23-5 package) PD 0 300 mW SOT23-5 package 6
Junction-to-ambient thermal resistance θJA 280 °C/W SOT23-5 package 6
Junction-to-case thermal resistance θJC 62 °C/W SOT23-5 package 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper by the bypass capacitor connection, the IN pin, and the GND pin of the system must be as small as possible. • It is recommended to use wide trace lengths or thick copper weight to minimize I×R drop an 13

CAD (KiCad official)

  • Symbol: TPL810F33-5TR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tpl810f33-5tr-etched.step / tpl810f33-5tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpl810f33-5tr.step / tpl810f33-5tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 3PEAK datasheet (19 pp, sha256 b2e3799d6e301ebe, retrieved 2026-11-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF