component
TPL740F33-5TR
Public Made by Adomby adom
3PEAK Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPL740F33-5TR
3PEAK · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPL740F33-5TR from 3PEAK, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input voltage pin; bypass IN to GND with a 1 μF or greater capacitor. |
| 2 | GND | power_in | Ground reference pin; connect the GND pin directly to the PCB ground plane. |
| 3 | EN | input | Regulator enable pin; drive EN high to turn the regulator on and low to turn it off, or connect EN to IN directly for automatic startup. |
| 4 | NC | unconnected | No connection on the fixed-output version; this pin is FB (feedback) only on the adjustable version. |
| 5 | OUT | power_out | Regulated output voltage pin; bypass OUT to GND with a 2.2 μF or greater capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 3PEAK |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.4 | 5.5 | V | 8 | ||
| Under-voltage lock-out threshold (VIN rising) | UVLO | 1.5 | 1.9 | 2.4 | V | VIN rising | 8 |
| Ground pin current | IGND | 49 | 200 | µA | IOUT = 0 mA | 8 | |
| Ground pin current | IGND | 200 | 2000 | µA | IOUT = 100 mA | 8 | |
| Shutdown current | ISHDN | 0.02 | 2 | nA | EN = GND | 8 | |
| EN logic-input high level (enable) | VIH(EN) | 1.2 | V | 8 | |||
| EN logic-input low level (disable) | VIL(EN) | 0 | 0.4 | V | 8 | ||
| EN pin leakage current | IEN | 1 | 3 | µA | EN = 5 V | 8 | |
| Output voltage accuracy | VOUT | -1 | 1 | % | TJ = +25°C | 8 | |
| Output voltage accuracy | VOUT | -2 | 2 | % | −40°C ≤ TJ ≤ +125°C | 8 | |
| Line regulation | ΔVOUT | 1 | 5 | mV | VIN = 2.4 V or VOUT(NOM) + 0.5 V to 5.5 V, or VIN ≥2.4 V, IOUT = 1 mA | 8 | |
| Load regulation | 20 | 60 | mV | IOUT = 1 mA to 500 mA | 8 | ||
| Dropout voltage | VDO | 75 | 100 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 100 mA | 8 | |
| Dropout voltage | VDO | 200 | 250 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 300 mA | 8 | |
| Dropout voltage | VDO | 300 | 400 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 500 mA | 8 | |
| Output current | IOUT | 0 | 500 | mA | VOUT in regulation | 8 | |
| Output current limit | ICL | 550 | 1000 | 1400 | mA | VOUT = 0.9 × VOUT(NOM) | 8 |
| Power supply rejection ratio (fixed version) | PSRR | 60 | dB | IOUT = 100 mA, f = 1 kHz | 9 | ||
| Power supply rejection ratio (fixed version) | PSRR | 40 | dB | IOUT = 100 mA, f = 100 kHz | 9 | ||
| Output noise voltage (fixed version) | VN | 130 | µVRMS | IOUT = 100 mA, BW = 100 Hz to 80 kHz | 9 | ||
| Start-up time (fixed version) | TSTR | 150 | µs | IOUT = 500 mA, COUT = 2.2 μF | 9 | ||
| Thermal shutdown temperature | TSD | 170 | ºC | 9 | |||
| Thermal shutdown hysteresis | 30 | ºC | 9 | ||||
| Hysteresis (UVLO) | 200 | mV | 8 | ||||
| VIN, VEN input voltage | VIN, VEN | -0.3 | 6 | V | 7 | ||
| VOUT output voltage | VOUT | -0.3 | 6 | V | 7 | ||
| Junction temperature range | TJ | -40 | 150 | °C | 7 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 7 | ||
| Lead temperature (soldering 10 sec) | TL | 260 | °C | Soldering 10 sec | 7 | ||
| Input voltage | VIN | 2.4 | 5.5 | V | 7 | ||
| Enable voltage | VEN | 0 | V | 7 | |||
| Output voltage | VOUT | 0 | 5 | V | 7 | ||
| Output current | IOUT | 0 | 500 | mA | 7 | ||
| Operating junction temperature range | TJ | -40 | 125 | °C | 7 | ||
| Junction-to-ambient thermal resistance (SOT23-5) | θJA | 280 | °C/W | SOT23-5 package | 7 | ||
| Junction-to-case thermal resistance (SOT23-5) | θJC | 62 | °C/W | SOT23-5 package | 7 |
CAD (KiCad official)
- Symbol:
TPL740F33-5TR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tpl740f33-5tr-etched.step/tpl740f33-5tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpl740f33-5tr.step/tpl740f33-5tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 3PEAK datasheet (22 pp, sha256
07a4d48905a56e33, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).