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Contents

README

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TPL7407LADR

Texas Instruments · Power Distribution Switches · SOIC-16

TPL7407LADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1 input Channel 1 GPIO input that drives output low to sink current when driven high (VIH ≥ 1.5V); compatible with 1.8V to 5V logic interfaces with 1MΩ internal pull-down.
2 IN2 input Channel 2 GPIO input that drives output low to sink current when driven high (VIH ≥ 1.5V); compatible with 1.8V to 5V logic interfaces with 1MΩ internal pull-down.
3 IN3 input Channel 3 GPIO input that drives output low to sink current when driven high (VIH ≥ 1.5V); compatible with 1.8V to 5V logic interfaces with 1MΩ internal pull-down.
4 IN4 input Channel 4 GPIO input that drives output low to sink current when driven high (VIH ≥ 1.5V); compatible with 1.8V to 5V logic interfaces with 1MΩ internal pull-down.
5 IN5 input Channel 5 GPIO input that drives output low to sink current when driven high (VIH ≥ 1.5V); compatible with 1.8V to 5V logic interfaces with 1MΩ internal pull-down.
6 IN6 input Channel 6 GPIO input that drives output low to sink current when driven high (VIH ≥ 1.5V); compatible with 1.8V to 5V logic interfaces with 1MΩ internal pull-down.
7 IN7 input Channel 7 GPIO input that drives output low to sink current when driven high (VIH ≥ 1.5V); compatible with 1.8V to 5V logic interfaces with 1MΩ internal pull-down.
8 GND power_in Ground reference pin; common return path for all output drain currents.
9 COM power_in Supply pin that powers gate drive circuitry; must be tied to 6.5V or higher (operating range 6.5V to 30V) for proper operation with internal LDO regulation to 5.3V.
10 OUT7 output Channel 7 low-side driver output that sinks current when input is driven high; rated for 600mA per channel with VOL = 210-900mV depending on drain current.
11 OUT6 output Channel 6 low-side driver output that sinks current when input is driven high; rated for 600mA per channel with VOL = 210-900mV depending on drain current.
12 OUT5 output Channel 5 low-side driver output that sinks current when input is driven high; rated for 600mA per channel with VOL = 210-900mV depending on drain current.
13 OUT4 output Channel 4 low-side driver output that sinks current when input is driven high; rated for 600mA per channel with VOL = 210-900mV depending on drain current.
14 OUT3 output Channel 3 low-side driver output that sinks current when input is driven high; rated for 600mA per channel with VOL = 210-900mV depending on drain current.
15 OUT2 output Channel 2 low-side driver output that sinks current when input is driven high; rated for 600mA per channel with VOL = 210-900mV depending on drain current.
16 OUT1 output Channel 1 low-side driver output that sinks current when input is driven high; rated for 600mA per channel with VOL = 210-900mV depending on drain current.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Power Management (PMIC)
Pins 16

CAD (KiCad official)

  • Symbol: TPL7407LADR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: tpl7407ladr-etched.step / tpl7407ladr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpl7407ladr.step / tpl7407ladr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 51b4243c936b3766, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF