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TPL730ADJ-5TR

Public Made by Adom

by adom

3PEAK Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPL730ADJ-5TR

3PEAK · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPL730ADJ-5TR from 3PEAK, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage pin. Bypass IN to GND with a 1 μF or greater capacitor. Input voltage range is 2.4 V to 5.5 V.
2 GND power_in Ground reference pin. Connect the GND pin to the PCB ground plane directly.
3 EN input Regulator enable pin. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to IN directly. EN high level is 1.2 V to VIN and low level is 0 V to 0.4 V.
4 FB input Output feedback pin (Adjustable version only). Connect to a resistor divider to adjust the output voltage; VFB is 0.8 V typical (0.784 V to 0.816 V).
5 OUT power_out Regulated output voltage pin. Bypass OUT to GND with a 2.2 μF or greater capacitor. Output is 0.8 V to 5 V for the adjustable version.

Key specifications

Parameter Value
Manufacturer 3PEAK
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage Range VIN 2.4 5.5 V 7
Output Voltage Accuracy VOUT -1 1 % TJ = +25°C 7
Output Voltage Accuracy VOUT -2 2 % −40°C ≤ TJ ≤ +125°C 7
Feedback Pin Voltage (ADJ version only) VFB 0.784 0.8 0.816 V 7
EN Logic-Input High Level (enable) VIH(EN) 1.2 V 7
EN Logic-Input Low Level (disable) VIL(EN) 0 0.4 V 7
Line Regulation ΔVOUT 1 5 mV VIN = 2.4 V or VOUT(NOM) + 0.5 V to 5.5 V, IOUT = 1 mA 7
Dropout Voltage VDO 200 250 mV VIN = 0.98 × VOUT(NOM), IOUT = 300 mA 7
Output Current IOUT 0 300 mA VOUT in regulation 7
Output Current Limit ICL 350 1000 1400 mA VOUT = 0.9 × VOUT(NOM) 7
Input Voltage (VIN, VEN) VIN, VEN -0.3 6 V Voltages with respect to GND 6
Output Voltage VOUT -0.3 6 V Voltages with respect to GND 6
Feedback Voltage (Adjustable version only) VFB -0.3 6 V Voltages with respect to GND 6
Junction Temperature Range TJ -40 150 °C 6
Storage Temperature Range TSTG -65 150 °C 6
Lead Temperature (Soldering 10 sec) TL 260 °C Soldering 10 sec 6
ESD Human Body Model HBM -8 8 kV ANSI ESDA JEDEC JS-001 6
ESD Charged Device Model CDM -2 2 kV ANSI ESDA JEDEC JS-002 6
Input Voltage VIN 2.4 5.5 V 6
Enable Voltage VEN 0 V Maximum is VIN 6
Output Voltage VOUT 0 5 V 6
Feedback Voltage (Adjustable version only) VFB 0 V Maximum is VOUT 6
Output Current IOUT 0 300 mA 6
Power Dissipation (SOT23-5 Package) PD 0 300 mW SOT23-5 package 6
Operating Junction Temperature Range TJ -40 125 °C 6
Junction-to-ambient thermal resistance θJA 280 °C/W SOT23-5 package 6
Junction-to-case thermal resistance θJC 62 °C/W SOT23-5 package 6
Ground Pin Current IGND 49 µA IOUT = 0 mA 7
Ground Pin Current IGND 200 µA IOUT = 100 mA 7
Shutdown Current ISHDN 20 nA EN = GND 7
VIN under-voltage Lock-out (rising) UVLO 1.9 V VIN rising 7
UVLO Hysteresis 200 mV 7
EN Pin Leakage Current IEN 1 μA EN = 5 V 7
Load Regulation 20 mV IOUT = 1 mA to 300 mA 7
Dropout Voltage VDO 75 mV VIN = 0.98 × VOUT(NOM), IOUT = 100 mA 7
Power Supply Rejection Ratio (ADJ version) PSRR 65 dB IOUT = 100 mA, f = 1 kHz, CBP = 100 nF 8
Power Supply Rejection Ratio (ADJ version) PSRR 60 dB IOUT = 100 mA, f = 100 kHz, CBP = 100 nF 8
Power Supply Rejection Ratio (ADJ version) PSRR 45 dB IOUT = 100 mA, f = 1 MHz, CBP = 100 nF 8
Output Noise Voltage (ADJ version) VN 40 μVRMS IOUT = 100 mA, BW = 100 Hz to 80 kHz, CBP = 100 nF 8
Start-up Time (ADJ version) TSTR 15 ms IOUT = 300 mA, COUT = 2.2 μF, CBP = 100 nF 8
Thermal Shutdown Temperature TSD 170 ºC 8
Thermal Shutdown Hysteresis 30 ºC 8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper by the bypass capacitor connection, IN pin and the GND pin of the system must be as small as possible. • It is recommended to use wide trace lengths or thick copper weight to minimize I×R drop and hea 14

CAD (KiCad official)

  • Symbol: TPL730ADJ-5TR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tpl730adj-5tr-etched.step / tpl730adj-5tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpl730adj-5tr.step / tpl730adj-5tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 3PEAK datasheet (21 pp, sha256 c8de456efa5ba9a5, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF