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TPL720F33-5TR

Public Made by Adom

by adom

3PEAK Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs tpl720f33-5tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json tpl720f33-5tr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray
README.md tpl720f33-5tr: specified limits as data (metadata.characteristics, 41 rows from the datasheet) · Ray
tpl720f33-5tr-etched.fit.json tpl720f33-5tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
tpl720f33-5tr-etched.glb tpl720f33-5tr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray
tpl720f33-5tr-etched.step tpl720f33-5tr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray
tpl720f33-5tr.glb Publish 0.1.0 · Ray
tpl720f33-5tr.kicad_mod Publish 0.1.0 · Ray
tpl720f33-5tr.kicad_sym Publish 0.1.0 · Ray
tpl720f33-5tr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
tpl720f33-5tr.step Publish 0.1.0 · Ray

TPL720F33-5TR

3PEAK · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPL720F33-5TR from 3PEAK, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage pin. Recommended operating range 2.4 V to 6 V (abs max 6.5 V). Bypass IN to GND with a 1 μF or greater ceramic capacitor placed close to the pin.
2 GND power_in Ground reference pin. Connect directly to the PCB ground plane to minimize impedance and improve thermal performance.
3 EN input Regulator enable input. Drive EN high (VIH ≥ 1.2 V, up to VIN) to turn the regulator on; drive low (VIL ≤ 0.4 V) to shut it down (ISHDN ≈ 0.1 μA). For automatic startup, tie EN to IN. EN pin leakage is ≤ 20 nA.
4 NC unconnected No internal connection. May be left floating or tied to GND for board layout convenience.
5 OUT power_out Regulated 3.3 V output pin (±1% at TJ = 25 °C, ±3% over −40 °C to +125 °C). Supplies up to 400 mA with 350 mV dropout at full load. Bypass OUT to GND with a 2.2 μF (up to 10 μF) low-ESR ceramic capacitor. Actively discharged through ~190 Ω when disabled.

Key specifications

Parameter Value
Manufacturer 3PEAK
Package SOT-23-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • TPL720F33-5TR
  • TPL720F33-5TR-3TR
  • TPL720F33-5TR-89TR
  • TPL720F33-5TR-FR

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 2.4 6 V 7
EN logic-input low level (disable) VIL(EN) 0 0.4 V 7
Output voltage accuracy VOUT -1 1 % IOUT = 30 mA, TJ = +25°C 7
Output voltage accuracy VOUT -3 3 % IOUT = 30 mA, –40°C ≤ TJ ≤ +125°C 7
Output current limit ICL 410 560 800 mA VOUT = 0.9 × VOUT(NOM) 7
Output current IOUT 0 400 mA VOUT in regulation 7
Input voltage VIN 2.4 6 V 6
Enable voltage VEN 0 V Upper limit printed as VIN 6
Output voltage VOUT 0 5 V 6
Output current IOUT 0 400 mA 6
Operating junction temperature range TJ -40 125 °C 6
Operating ambient temperature range TA -40 85 °C 6
Input voltage (VIN, VEN) VIN, VEN -0.3 6.5 V With respect to GND 6
Output voltage VOUT -0.3 6.5 V With respect to GND 6
Junction temperature range TJ -40 150 °C 6
Storage temperature range TSTG -65 150 °C 6
Lead temperature (soldering 10 sec) TL 260 °C Soldering 10 sec 6
ESD Human Body Model HBM -4 4 kV ANSI/ESDA/JEDEC JS-001 6
ESD Charged Device Model CDM -1 1 kV ANSI/ESDA/JEDEC JS-002 6
Ground pin current IGND 1.4 µA IOUT = 0 mA 7
Ground pin current IGND 2.8 µA IOUT = 1 mA 7
Shutdown current ISHDN 0.1 µA EN = GND (4-/5-Pin Package Only) 7
VIN under-voltage lock-out, rising UVLO 1.8 V VIN rising 7
VIN under-voltage lock-out hysteresis UVLO 200 mV Hysteresis 7
EN pin leakage current IEN 20 nA EN = VIN 7
Line regulation ΔVOUT 3 mV VIN = VOUT(NOM) + 2 V to 6 V, or VIN ≥ 2.4V, IOUT = 1 mA 7
Load regulation ΔVOUT 40 mV IOUT = 1 mA to 400 mA 7
Dropout voltage VDO 80 mV VIN = 0.98 × VOUT(NOM), IOUT = 100 mA 7
Dropout voltage VDO 170 mV VIN = 0.98 × VOUT(NOM), IOUT = 200 mA 7
Dropout voltage VDO 350 mV VIN = 0.98 × VOUT(NOM), IOUT = 400 mA 7
Output discharge resistance RDIS 190 Ω VIN = VOUT(NOM) + 2 V, EN = GND 7
Power supply rejection ratio PSRR 55 dB IOUT = 10 mA, f = 100 Hz, COUT = 2.2 µF 7
Power supply rejection ratio PSRR 54 dB IOUT = 10 mA, f = 1 kHz, COUT = 2.2 µF 7
Power supply rejection ratio PSRR 50 dB IOUT = 10 mA, f = 10 kHz, COUT = 2.2 µF 7
Power supply rejection ratio PSRR 53 dB IOUT = 10 mA, f = 1 MHz, COUT = 2.2 µF 7
Output noise voltage VN 90 µVRMS IOUT = 10 mA, BW = 10Hz to 100 kHz 7
Start-up time from EN assertion to 0.98 × VOUT(NOM) tSTR 680 µs IOUT = 200 mA, COUT = 2.2 µF 7
Thermal shutdown temperature TSD 165 ºC 7
Thermal shutdown hysteresis TSD 15 ºC 7
Junction-to-ambient thermal resistance θJA 280 °C/W SOT23-5 package 6
Junction-to-case thermal resistance θJC 62 °C/W SOT23-5 package 6

CAD (KiCad official)

  • Symbol: TPL720F33-5TR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tpl720f33-5tr-etched.step / tpl720f33-5tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpl720f33-5tr.step / tpl720f33-5tr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tpl720f33-5tr.step 85 KB You want the bare part, or you mark your own boards.
tpl720f33-5tr-etched.step 2.1 MB You want the part with TPL720F33-5TR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 530 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 3PEAK datasheet (18 pp, sha256 c65dff82814441be, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF