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TPL710F33-5TR

Public Made by Adom

by adom

3PEAK Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPL710F33-5TR

3PEAK · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPL710F33-5TR from 3PEAK, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage pin, operating range 2.4 V to 6 V; bypass IN to GND with a 1 µF or greater capacitor.
2 GND power_in Ground reference pin; connect directly to the PCB ground plane.
3 EN input Active-high regulator enable: drive high to turn on and low to turn off (VIH min 1.2 V, VIL max 0.4 V); connect to IN for automatic startup.
4 NC unconnected No connection.
5 OUT power_out Regulated output voltage pin, up to 200 mA; bypass OUT to GND with a 2.2 µF or greater capacitor.

Key specifications

Parameter Value
Manufacturer 3PEAK
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage Range VIN 2.4 6 V 7
Ground Pin Current IGND 1.4 8 µA IOUT = 0 mA, -40°C ≤ TJ ≤ +105°C 7
Ground Pin Current IGND 30 µA IOUT = 0 mA, -40°C ≤ TJ ≤ +125°C 7
Ground Pin Current IGND 500 µA VIN = 5 V, IOUT = 200 mA 7
Shutdown Current ISHDN 0.1 3 µA EN = GND, -40°C ≤ TJ ≤ +105°C 7
Shutdown Current ISHDN 5 µA EN = GND, -40°C ≤ TJ ≤ +125°C 7
EN Logic-input High Level (Enable) VIH (EN) 1.2 V 7
EN Logic-input Low Level (Disable) VIL (EN) 0 0.4 V 7
EN Pin Leakage Current IEN 20 nA EN = VIN 7
Output Voltage Accuracy VOUT -1 1 % IOUT = 30 mA, TJ = +25°C 7
Output Voltage Accuracy VOUT -3 3 % IOUT = 30 mA, -40°C ≤ TJ ≤ +125°C 7
Line Regulation VREF_I 3 mV VIN = VOUT (NOM) + 1 V to 6 V, or VIN ≥2.4V, IOUT = 1 mA 7
Load Regulation 40 mV IOUT = 1 mA to 200 mA 7
Dropout Voltage VDO 40 mV IOUT 7
Dropout Voltage VDO 80 mV VIN = 0.98 × VOUT (NOM), IOUT = 100 mA 7
Dropout Voltage VDO 170 mV VIN = 0.98 × VOUT (NOM), IOUT = 200 mA 8
Output Current IOUT 0 200 mA VOUT in Regulation 8
Output Current limit ICL 300 560 800 mA VOUT = 0.9 × VOUT (NOM) 8
Output Discharge Resistance RDIS 190 Ω VIN = VOUT (NOM) + 1 V, EN = GND 8
Power Supply Rejection Ratio PSRR 55 dB IOUT = 10 mA, f = 100 Hz, COUT = 2.2 µF 8
Power Supply Rejection Ratio PSRR 54 dB IOUT = 10 mA, f = 1 kHz, COUT = 2.2 µF 8
Power Supply Rejection Ratio PSRR 50 dB IOUT = 10 mA, f = 10 kHz, COUT = 2.2 µF 8
Power Supply Rejection Ratio PSRR 53 dB IOUT = 10 mA, f = 1 MHz, COUT = 2.2 µF 8
Output Noise Voltage VN 90 µVRMS IOUT = 10 mA, BW = 10Hz to 100 kHz 8
Start-up Time from EN TSTR 680 µs Assertion to 0.98 × VOUT (NOM), IOUT= 200 mA, COUT = 2.2 μF 8
UVLO VIN Rising 1.8 V VIN Rising 7
UVLO Hysteresis 200 mV Hysteresis 7
Thermal Shutdown Temperature TSD 165 ºC 8
Thermal Shutdown Hysteresis 15 ºC 8
VIN, VEN Input Voltage VIN, VEN -0.3 6.5 V Voltages with respect to GND 6
VOUT Output Voltage VOUT -0.3 6.5 V Voltages with respect to GND 6
TJ Junction Temperature Range TJ -40 150 °C 6
TSTG Storage Temperature Range TSTG -65 150 °C 6
TL Lead Temperature (Soldering 10 sec) TL 260 °C Soldering 10 sec 6
ESD Human Body Model HBM -4 4 kV ANSI/ESDA/JEDEC JS-001 6
ESD Charged Device Model CDM -1 1 kV ANSI/ESDA/JEDEC JS-002 6
VIN Input Voltage VIN 2.4 6 V 6
VEN Enable Voltage VEN 0 V Maximum printed as VIN 6
VOUT Output Voltage VOUT 0 5 V 6
IOUT Output Current IOUT 0 200 mA 6
TJ Operating Junction Temperature Range TJ -40 125 °C 6
Junction-to-ambient thermal resistance θJA 280 °C/W SOT23-5 package 6
Junction-to-case thermal resistance θJC 62 °C/W SOT23-5 package 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper bypass capacitor connection, the IN pin, and the GND pin of the system must be as small as possible. • It is recommended to use wide and thick copper to minimize I×R drop and heat dissipation. 15

CAD (KiCad official)

  • Symbol: TPL710F33-5TR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tpl710f33-5tr-etched.step / tpl710f33-5tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpl710f33-5tr.step / tpl710f33-5tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 3PEAK datasheet (22 pp, sha256 beafa4546969f4ab, retrieved 2026-11-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF