TPL5100DGSR

Texas Instruments · Timers / Counters · MSOP-10

TPL5100DGSR from Texas Instruments, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D0	input	Logic input that sets the timer delay period (tDP) together with D1 and D2; connect to GND for logic low or to VDD for logic high.
2	D1	input	Logic input that sets the timer delay period (tDP) together with D0 and D2; connect to GND for logic low or to VDD for logic high.
3	D2	input	Logic input that sets the timer delay period (tDP) together with D0 and D1; connect to GND for logic low or to VDD for logic high.
4	VDD	power_in	Supply voltage pin, with recommended operating supply range of 1.8 V to 5.0 V (VDD-GND) and absolute maximum of -0.3 V to 6 V.
5	GND	power_in	Ground reference pin for the device; all voltages are referenced to this pin.
6	DONE	input	Logic input for the watchdog function; a DONE pulse must be at least 100 ns wide and must arrive before the end of the MOS_DRV pulse, with VIH of 0.7xVDD and VIL of 0.3xVDD.
7	TCAL	output	Short calibration output pulse, nominally 15.625 ms (range 14.063 ms to 17.188 ms), used to estimate the actual timer delay period.
8	MOS_DRV	output	Drives the external MOSFET that power-cycles the remaining system, with a 31.25 ms MOS_DRV pulse width and output levels of VDD-0.3 V (high, at 100 µA) and 0.3 V (low, at -100 µA) as specified.
9	DNC	unconnected	Do Not Connect pin; leave floating.
10	PGOOD	input	Digital power-good input from the battery management IC; a low level resets the internal counter and holds the microcontroller off, with VIH of 0.7xVDD and VIL of 0.3xVDD.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	MSOP-10
Category	Clock/Timing
Pins	10

CAD (KiCad official)

Symbol: TPL5100DGSR
Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
3D model: MSOP-10 (KiCad packages3D, STEP)
3D model files: tpl5100dgsr-etched.step / tpl5100dgsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpl5100dgsr.step / tpl5100dgsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (21 pp, sha256 14147dbe08d9741c, retrieved 2026-10-10, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TPL5100DGSR

**Texas Instruments** · Timers / Counters · MSOP-10

TPL5100DGSR from Texas Instruments, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D0 | input | Logic input that sets the timer delay period (tDP) together with D1 and D2; connect to GND for logic low or to VDD for logic high. |
| 2 | D1 | input | Logic input that sets the timer delay period (tDP) together with D0 and D2; connect to GND for logic low or to VDD for logic high. |
| 3 | D2 | input | Logic input that sets the timer delay period (tDP) together with D0 and D1; connect to GND for logic low or to VDD for logic high. |
| 4 | VDD | power_in | Supply voltage pin, with recommended operating supply range of 1.8 V to 5.0 V (VDD-GND) and absolute maximum of -0.3 V to 6 V. |
| 5 | GND | power_in | Ground reference pin for the device; all voltages are referenced to this pin. |
| 6 | DONE | input | Logic input for the watchdog function; a DONE pulse must be at least 100 ns wide and must arrive before the end of the MOS_DRV pulse, with VIH of 0.7xVDD and VIL of 0.3xVDD. |
| 7 | TCAL | output | Short calibration output pulse, nominally 15.625 ms (range 14.063 ms to 17.188 ms), used to estimate the actual timer delay period. |
| 8 | MOS_DRV | output | Drives the external MOSFET that power-cycles the remaining system, with a 31.25 ms MOS_DRV pulse width and output levels of VDD-0.3 V (high, at 100 µA) and 0.3 V (low, at -100 µA) as specified. |
| 9 | DNC | unconnected | Do Not Connect pin; leave floating. |
| 10 | PGOOD | input | Digital power-good input from the battery management IC; a low level resets the internal counter and holds the microcontroller off, with VIH of 0.7xVDD and VIL of 0.3xVDD. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | MSOP-10 |
| Category | Clock/Timing |
| Pins | 10 |

## CAD (KiCad official)

- Symbol: `TPL5100DGSR`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files: `tpl5100dgsr-etched.step` / `tpl5100dgsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpl5100dgsr.step` / `tpl5100dgsr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tpl5100) (21 pp, sha256 `14147dbe08d9741c`, retrieved 2026-10-10, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tpl5100dgsr-datasheet.pdf)