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TPL1401DSGR
Public Made by Adomby adom
Texas Instruments Digital Potentiometers, WSON-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPL1401DSGR
Texas Instruments · Digital Potentiometers · WSON-8-EP(2x2)
TPL1401DSGR from Texas Instruments, in a WSON-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Four-state address input for the device. |
| 2 | SCL | input | Serial interface clock that must be connected to the supply voltage with an external pullup resistor. |
| 3 | SDA | bidirectional | Bidirectional data pin that clocks data into or out of the input register and must be connected to the supply voltage with an external pullup resistor. |
| 4 | CAP | input | External capacitor pin for the internal LDO, requiring a capacitor of around 1.5 µF between CAP and AGND. |
| 5 | AGND | power_in | Ground reference point for all circuitry on the device. |
| 6 | VDD | power_in | Analog supply voltage input rated 1.8 V to 5.5 V, also used as the reference input. |
| 7 | FB | input | Voltage feedback pin. |
| 8 | OUT | output | Analog output voltage from the digipot buffer. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-8-EP(2x2) |
| Category | ADC/DAC/Data Conversion |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage / reference, VDD to AGND | VDD | -0.3 | 6 | V | VDD to AGND | 4 | |
| Digital input(s) to AGND | -0.3 | V | Digital input(s) to AGND; printed max VDD + 0.3 V | 4 | |||
| CAP to AGND | CAP | -0.3 | 1.65 | V | CAP to AGND | 4 | |
| VFB to AGND | VFB | -0.3 | V | VFB to AGND; printed max VDD + 0.3 V | 4 | ||
| VOUT to AGND | VOUT | -0.3 | V | VOUT to AGND; printed max VDD + 0.3 V | 4 | ||
| Current into any pin | -10 | 10 | mA | 4 | |||
| Junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Positive supply voltage to ground (AGND) | VDD | 1.71 | 5.5 | V | 4 | ||
| Digital input high voltage | VIH | 1.62 | V | 1.7 V < VDD ≤ 5.5 V | 4 | ||
| Digital input low voltage | VIL | 0.4 | V | 4 | |||
| Ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Integral nonlinearity (relative accuracy) | INL | -1 | 1 | LSB | 5 | ||
| Differential nonlinearity | DNL | -1 | 1 | LSB | 5 | ||
| Zero code error | 6 | 12 | mV | Code 0d into digipot | 5 | ||
| Zero code error | 6 | 15 | mV | Internal VREF, gain = 4x, VDD = 5.5 V | 5 | ||
| Zero code error temperature coefficient | -10 | 10 | µV/°C | 5 | |||
| Offset error | -0.5 | 0.25 | 0.5 | %FSR | VREF tied to VDD, measured between end-point codes 2d and 254d, output unloaded | 5 | |
| Offset error temperature coefficient | -0.0003 | 0.0003 | %FSR/°C | VREF tied to VDD, measured between end-point codes 2d and 254d, output unloaded | 5 | ||
| Gain error | -0.5 | 0.25 | 0.5 | %FSR | VREF tied to VDD, measured between end-point codes 2d and 254d, output unloaded | 5 | |
| Gain error temperature coefficient | -0.0008 | 0.0008 | %FSR/°C | VREF tied to VDD, measured between end-point codes 2d and 254d, output unloaded | 5 | ||
| Full scale error | -1 | 0.5 | 1 | %FSR | 1.8 V ≤ VDD < 2.7 V, code 511d into digipot, no headroom | 5 | |
| Full scale error | -0.5 | 0.25 | 0.5 | %FSR | 2.7 V ≤ VDD ≤ 5.5 V, code 511d into digipot, no headroom | 5 | |
| Full scale error temperature coefficient | -0.0008 | 0.0008 | %FSR/°C | 5 | |||
| Output voltage | VOUT | 0 | 5.5 | V | Reference tied to VDD | 5 | |
| Capacitive load | CL | 1 | nF | RL = Infinite, phase margin = 30° | 5 | ||
| Capacitive load | CL | 2 | nF | RL = 5 kΩ, phase margin = 30° | 5 | ||
| VFB dc output impedance | ZO | 160 | 200 | 240 | kΩ | Digipot output enabled | 5 |
| Load capacitor - CAP pin | 0.5 | 15 | µF | 6 | |||
| Current flowing into VDD | IDD | 0.5 | 0.8 | mA | Normal mode, digipot at full scale, digital pins static | 6 | |
| Junction-to-ambient thermal resistance | RθJA | 49 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 50 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 24.1 | °C/W | 4 | |||
| Junction-to-top characterization parameter | ΨJT | 1.1 | °C/W | 4 | |||
| Junction-to-board characterization parameter | ΨJB | 24.1 | °C/W | 4 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 8.7 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
TPL1401DSGR - Footprint:
Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm - 3D model: WSON-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
tpl1401dsgr-etched.step/tpl1401dsgr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpl1401dsgr.step/tpl1401dsgr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (41 pp, sha256
c82f7727cc4730f4, retrieved 2026-11-02, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).