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TPIC74101QPWPRQ1
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Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPIC74101QPWPRQ1
Texas Instruments · DC-DC Converters · HTSSOP-20-EP
TPIC74101QPWPRQ1 from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCR1 | input | Programmable slew-rate control input; logic-level limits are 0 V to 5.25 V, or V(logic) when connected directly to V(logic). |
| 2 | Cboot2 | input | External bootstrap capacitor connection, with a recommended bootstrap voltage of 8 V and an absolute maximum of 14 V. |
| 3 | Cboot1 | input | External bootstrap capacitor connection, with a recommended bootstrap voltage of V(driver) + 10 V and an absolute maximum of 52 V. |
| 4 | Vdriver | power_in | Unregulated input voltage source, recommended 6 V to 24 V with an absolute maximum of 40 V. |
| 5 | L1 | passive | Inductor input; an external Schottky diode to GND must be connected to L1, with a maximum forward drop of 0.4 V at 1 A and 125 °C, and V(L1) is recommended between -1 V and 17 V. |
| 6 | PGND | power_in | Power ground pin for the switch-mode power stage. |
| 7 | L2 | passive | Inductor output; recommended V(L2) is 5 V to 5.5 V with an absolute maximum range of -1 V to 7 V. |
| 8 | VOUT | power_out | Regulated 5-V output, held to 5 V ±2% in buck mode. |
| 9 | 5Vg | power_out | Switched 5-V regulated output with current limiting, rated for 1 A load current (200 mA at a 2 V Vdriver input and 120 mA at a 1.5 V Vdriver input). |
| 10 | AIN | input | Programmable alarm setting input; unregulated input voltage range is 0 V to 24 V. |
| 11 | CLP | bidirectional | Low-power operation mode digital I/O; logic levels limited to 0 V to 5.25 V, or V(logic) when connected directly to V(logic). |
| 12 | RESET | output | Open-drain reset output that indicates when the 5-V rail is out of tolerance; logic levels limited to 0 V to 5.25 V with an absolute maximum of 7 V. |
| 13 | AOUT | output | Open-drain alarm output that is activated when Vdriver falls below the threshold set by AIN; logic levels limited to 0 V to 5.25 V. |
| 14 | REST | output | Programmable reset timer delay pin, where the delay is set by an external timing capacitor; logic levels limited to 0 V to 5.25 V. |
| 15 | Rmod | input | Main switching-frequency modulation setting used to minimize EMI; logic levels limited to 0 V to 5.25 V. |
| 16 | GND | power_in | Ground reference pin for the device; the exposed thermal pad should also be connected to GND or left floating. |
| 17 | Vlogic | power_out | Supply decoupling output that may be used as a 5-V supply for logic-level inputs. |
| 18 | ENABLE | input | Switch-mode regulator enable/disable input; unregulated input voltage range is 0 V to 24 V with an absolute maximum of 40 V. |
| 19 | 5Vg_ENABLE | input | Enable/disable input for the switched 5-V regulator output; logic levels limited to 0 V to 5.25 V. |
| 20 | SCR0 | input | Programmable slew-rate control input; logic-level limits are 0 V to 5.25 V, or V(logic) when connected directly to V(logic). |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Supply Chip |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPIC74101QPWPRQ1 - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tpic74101qpwprq1-etched.step/tpic74101qpwprq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpic74101qpwprq1.step/tpic74101qpwprq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
60e8240332c7b939, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).