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TPIC6C596DR

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Texas Instruments Shifting Register, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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TPIC6C596DR

Texas Instruments · Shifting Register · SOP-16

TPIC6C596DR from Texas Instruments, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Logic supply voltage. Recommended operating range 4.5 V to 5.5 V (absolute max 7 V).
2 SER IN input Serial data input. Clocked into the 8-bit shift register on the rising edge of SRCK. Setup/hold time 15 ns.
3 DRAIN0 output Open-drain low-side DMOS transistor output, bit 0. 33 V VDS clamp, 100 mA continuous / 250 mA current-limited sink capability. Off when output enable G is high.
4 DRAIN1 output Open-drain low-side DMOS transistor output, bit 1. 33 V clamp, 100 mA continuous sink.
5 DRAIN2 output Open-drain low-side DMOS transistor output, bit 2. 33 V clamp, 100 mA continuous sink.
6 DRAIN3 output Open-drain low-side DMOS transistor output, bit 3. 33 V clamp, 100 mA continuous sink.
7 CLR input Active-low shift-register clear. When low, all bits in the shift register are cleared.
8 G input Active-low output enable. When high, all output buffers are held low and DMOS drains are off. When low, storage register data drives the output buffers.
9 SER OUT output Serial data output clocked out on the falling edge of SRCK. Used to cascade multiple TPIC6C596 devices. VOH ≥ 4.4 V @ IOH = -20 μA, VCC = 4.5 V.
10 RCK input Register (latch) clock. Rising edge transfers the shift-register contents into the 8-bit D-type storage (output) register.
11 DRAIN4 output Open-drain low-side DMOS transistor output, bit 4. 33 V clamp, 100 mA continuous sink.
12 DRAIN5 output Open-drain low-side DMOS transistor output, bit 5. 33 V clamp, 100 mA continuous sink.
13 DRAIN6 output Open-drain low-side DMOS transistor output, bit 6. 33 V clamp, 100 mA continuous sink.
14 DRAIN7 output Open-drain low-side DMOS transistor output, bit 7 (MSB). 33 V clamp, 100 mA continuous sink.
15 SRCK input Shift-register clock. Rising edge shifts SER IN into the 8-bit shift register; falling edge clocks SER OUT. Maximum 10 MHz.
16 GND power_in Power ground. Common return for logic supply and open-drain DMOS transistor sources (each DMOS source is internally connected to GND).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • TPIC6C596DR
  • TPIC6C596DRD
  • TPIC6C596DRN
  • TPIC6C596DRPW
  • TPIC6C596DRPWR

CAD (KiCad official)

  • Symbol: TPIC6C596DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: tpic6c596dr-etched.step / tpic6c596dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpic6c596dr.step / tpic6c596dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 a2fc58849952edbb, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF