TPIC6C595N

{
  "slug": "tpic6c595n",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Shifting Register, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic ics",
    "tpic6c595n",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "tpic6c595n.kicad_sym",
    "tpic6c595n.kicad_mod",
    "tpic6c595n.glb",
    "tpic6c595n.step",
    "tpic6c595n.lbr",
    "docs/hero.png",
    "docs/tpic6c595n-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "tpic6c595n-hero.glb",
    "tpic6c595n-hero.overlay.json",
    "tpic6c595n-etched.glb"
  ],
  "component": {
    "mpn": "TPIC6C595N",
    "manufacturer": "Texas Instruments",
    "package": "PDIP-16",
    "pin_count": 16,
    "category": "Logic ICs",
    "subcategory": "Shifting Register",
    "datasheet": "https://www.ti.com/lit/ds/symlink/tpic6c595n.pdf",
    "parts": {
      "symbol": "tpic6c595n.kicad_sym",
      "footprint": "tpic6c595n.kicad_mod",
      "model_3d": "tpic6c595n-hero.glb",
      "model_3d_plain": "tpic6c595n-etched.glb",
      "model_3d_step": "tpic6c595n-etched.step",
      "model_3d_step_plain": "tpic6c595n.step",
      "lbr": "tpic6c595n.lbr"
    },
    "distributor_links": {
      "lcsc": "C2862263",
      "digikey": "2156-TPIC6C595N-ND",
      "mouser": "595-TPIC6C595N"
    },
    "distributor_check": {
      "checked_at": "2026-10-26T06:46:40Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "2156-TPIC6C595N-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-TPIC6C595N",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VCC",
        "type": "power_in",
        "description": "Logic supply input; recommended VCC is 4.5 V to 5.5 V, and the absolute maximum logic supply voltage is 7 V with respect to GND."
      },
      {
        "number": "2",
        "name": "SER IN",
        "type": "input",
        "description": "Serial data input to the 8-bit shift register, which needs 20 ns setup and 20 ns hold relative to the rising edge of SRCK."
      },
      {
        "number": "3",
        "name": "DRAIN0",
        "type": "output",
        "description": "Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C."
      },
      {
        "number": "4",
        "name": "DRAIN1",
        "type": "output",
        "description": "Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C."
      },
      {
        "number": "5",
        "name": "DRAIN2",
        "type": "output",
        "description": "Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C."
      },
      {
        "number": "6",
        "name": "DRAIN3",
        "type": "output",
        "description": "Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C."
      },
      {
        "number": "7",
        "name": "CLR",
        "type": "input",
        "description": "Shift register clear, active-low; when CLR is low the input shift register is cleared."
      },
      {
        "number": "8",
        "name": "G",
        "type": "input",
        "description": "Output enable, active-low; when held high, all data in the output buffers is held low and all drain outputs are off."
      },
      {
        "number": "9",
        "name": "SER OUT",
        "type": "output",
        "description": "Serial data output that shifts data out on the rising edge of SRCK, allowing cascading to additional devices."
      },
      {
        "number": "10",
        "name": "RCK",
        "type": "input",
        "description": "Register clock; data transfers from the shift register to the 8-bit storage register on its rising edge."
      },
      {
        "number": "11",
        "name": "DRAIN4",
        "type": "output",
        "description": "Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C."
      },
      {
        "number": "12",
        "name": "DRAIN5",
        "type": "output",
        "description": "Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C."
      },
      {
        "number": "13",
        "name": "DRAIN6",
        "type": "output",
        "description": "Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C."
      },
      {
        "number": "14",
        "name": "DRAIN7",
        "type": "output",
        "description": "Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C."
      },
      {
        "number": "15",
        "name": "SRCK",
        "type": "input",
        "description": "Shift register clock; data shifts through the shift register on its rising edge."
      },
      {
        "number": "16",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; all voltages are referenced to GND and each power DMOS source is internally connected to GND."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The DRAIN outputs are open-drain DMOS transistors, which KiCad's open_collector class is closer to, ; VCC and GND are listed as I and power ground in the pin table. VCC is typed power_in and GND is type; The setup and hold times for SER IN and the functional descriptions of CLR, G, RCK and SRCK combine "
        ],
        "pages_sent": 8,
        "cost_usd": 0.0462,
        "at": "2026-10-26T06:46:28"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/tpic6c595n.pdf",
        "pages": 30,
        "sha256": "90296cb6d9caf791",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          7.874,
          19.177,
          6.98
        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "17a30b1f0ab3fd5384a1231e3c63c394888d5b952c542a8c189e023ed3467464",
        "checked": "2026-10-26",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "tpic6c595n-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
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        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
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        "sha256": "e2ecb6e8f62d6f71f7a32c3c2743784b1f8823885cd7dba3beb233db7cb91cfe",
        "checked": "2026-10-26",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}