component

TPIC6C595N

Public Made by Adom

by adom

Texas Instruments Shifting Register, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icstpic6c595nfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
tpic6c595n / README.md
History Download
Ray Publish 0.1.0 b5bb671 5d ago

TPIC6C595N

Texas Instruments · Shifting Register · PDIP-16

TPIC6C595N from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Logic supply input; recommended VCC is 4.5 V to 5.5 V, and the absolute maximum logic supply voltage is 7 V with respect to GND.
2 SER IN input Serial data input to the 8-bit shift register, which needs 20 ns setup and 20 ns hold relative to the rising edge of SRCK.
3 DRAIN0 output Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C.
4 DRAIN1 output Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C.
5 DRAIN2 output Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C.
6 DRAIN3 output Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C.
7 CLR input Shift register clear, active-low; when CLR is low the input shift register is cleared.
8 G input Output enable, active-low; when held high, all data in the output buffers is held low and all drain outputs are off.
9 SER OUT output Serial data output that shifts data out on the rising edge of SRCK, allowing cascading to additional devices.
10 RCK input Register clock; data transfers from the shift register to the 8-bit storage register on its rising edge.
11 DRAIN4 output Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C.
12 DRAIN5 output Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C.
13 DRAIN6 output Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C.
14 DRAIN7 output Open-drain low-side power DMOS output rated 33 V drain-to-source, with 100 mA continuous and 250 mA maximum current limit at TC = 25°C.
15 SRCK input Shift register clock; data shifts through the shift register on its rising edge.
16 GND power_in Power ground; all voltages are referenced to GND and each power DMOS source is internally connected to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Logic supply voltage VCC 4.5 5.5 V 4
Operating case temperature TC -40 125 °C 4
Pulsed drain output current 250 mA TC = 25°C, VCC = 5 V, all outputs on; pulse duration ≤ 100 μs, duty cycle ≤ 2% 4
Setup time, SER IN high before SRCK↑ tsu 20 ns see Figure 9 4
Hold time, SER IN high after SRCK↑ th 20 ns see Figure 9 4
Pulse duration tw 40 ns see Figure 9 4
Logic supply voltage VCC -0.3 7 V 4
Logic input voltage VI -0.3 7 V 4
Power DMOS drain-to-source voltage VDS -0.3 33 V 4
Continuous source-to-drain diode anode current 0 250 mA 4
Pulsed source-to-drain diode anode current 0 500 mA pulse duration ≤ 100 μs and duty cycle ≤ 2% 4
Pulsed drain current, each output, all outputs on ID 0 250 mA TC = 25°C 4
Continuous drain current, each output, all outputs on ID 0 100 mA TC = 25°C 4
Peak drain current single output IDM 0 250 mA TC = 25°C 4
Single-pulse avalanche energy EAS 0 30 mJ see Figure 11 4
Avalanche current IAS 0 200 mA DRAIN supply voltage = 15 V, TJS = 25°C, L = 1.5 H, IAS = 200 mA 4
Operating virtual junction temperature TJ -40 150 °C 4
Operating case temperature TC -40 125 °C 4
Storage temperature Tstg -65 150 °C 4
Junction-to-ambient thermal resistance RθJA 51.5 °C/W N (PDIP) package, 16 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 31.4 °C/W N (PDIP) package, 16 pins 5
Junction-to-board thermal resistance RθJB 38.8 °C/W N (PDIP) package, 16 pins 5
Junction-to-top characterization parameter ψJT 23.6 °C/W N (PDIP) package, 16 pins 5
Junction-to-board characterization parameter ψJB 31.3 °C/W N (PDIP) package, 16 pins 5
Drain-to-source breakdown voltage V(BR)DSX 33 37 V ID = 1 mA 5
Source-to-drain diode forward voltage VSD 0.85 1.2 V IF = 100 mA 5
High-level output voltage, SER OUT VOH 4.4 4.49 V IOH = −20 µA, VCC = 4.5 V 5
High-level output voltage, SER OUT VOH 4 4.2 V IOH = −4 mA, VCC = 4.5 V 5
Low-level output voltage, SER OUT VOL 0.005 0.1 V IOL = 20 µA, VCC = 4.5 V 5
Low-level output voltage, SER OUT VOL 0.3 0.5 V IOL = 4 mA, VCC = 4.5 V 5
High-level input current IIH 1 µA VCC = 5.5 V, VI = VCC 5
Low-level input current IIL -1 µA VCC = 5.5 V, VI = 0 5
Logic supply current, all outputs off ICC 20 200 µA VCC = 5.5 V, all outputs off 5
Logic supply current, all outputs on ICC 150 500 µA VCC = 5.5 V, all outputs on 5
Logic supply current at frequency ICC(FRQ) 1.2 5 mA fSRCK = 5 MHz, CL = 30 pF, all outputs off 5
Nominal current IN 90 mA VDS(on) = 0.5 V, IN = ID, TC = 85°C 5
Off-state drain current IDSX 0.1 0.2 µA VDS = 30 V, VCC = 5.5 V 5
Off-state drain current IDSX 0.15 0.3 µA VDS = 30 V, VCC = 5.5 V, TC = 125°C 5
Static drain-source on-state resistance rDS(on) 6.5 9 Ω ID = 50 mA, VCC = 4.5 V 5
Static drain-source on-state resistance rDS(on) 9.9 12 Ω ID = 50 mA, TC = 125°C, VCC = 4.5 V 5
Static drain-source on-state resistance rDS(on) 6.8 10 Ω ID = 100 mA, VCC = 4.5 V 5
Propagation delay time, low-to-high-level output from G tPLH 80 ns VCC = 5 V, TC = 25°C 6
Propagation delay time, high-to-low-level output from G tPHL 50 ns VCC = 5 V, TC = 25°C 6
Propagation delay time, SRCK↓ to SER OUT tpd 15 ns VCC = 5 V, TC = 25°C 6
Rise time, drain output tr 100 ns VCC = 5 V, TC = 25°C 6
Fall time, drain output tf 80 ns VCC = 5 V, TC = 25°C 6
Reverse-recovery time trr 120 ns VCC = 5 V, TC = 25°C; IF = 100 mA, di/dt = 10 A/µs 6

CAD (KiCad official)

  • Symbol: TPIC6C595N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: PDIP-16 (KiCad packages3D, STEP)
  • 3D model files: tpic6c595n-etched.step / tpic6c595n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpic6c595n.step / tpic6c595n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 90296cb6d9caf791, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF