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TPIC6B595N

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Texas Instruments Shift Registers, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPIC6B595N

Texas Instruments · Shift Registers · PDIP-20

TPIC6B595N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection; leave this pin unconnected.
2 VCC power_in Logic supply voltage, recommended operating range 4.5 V to 5.5 V, with a ceramic bypass capacitor placed close to this pin.
3 SER IN input Serial data input to the 8-bit shift register, sampled on the rising edge of SRCK with setup and hold times of 20 ns minimum; logic high requires at least 0.85 VCC and logic low at most 0.15 VCC.
4 DRAIN0 output Low-side open-drain power DMOS output rated for 50 V drain-to-source and 150 mA continuous sink current, with typical 500 mA current limit at TC = 25°C.
5 DRAIN1 output Low-side open-drain power DMOS output rated for 50 V drain-to-source and 150 mA continuous sink current, with typical 500 mA current limit at TC = 25°C.
6 DRAIN2 output Low-side open-drain power DMOS output rated for 50 V drain-to-source and 150 mA continuous sink current, with typical 500 mA current limit at TC = 25°C.
7 DRAIN3 output Low-side open-drain power DMOS output rated for 50 V drain-to-source and 150 mA continuous sink current, with typical 500 mA current limit at TC = 25°C.
8 SRCLR input Active-low shift register clear that clears all registers in the device; TI recommends clearing the device during power-up or initialization.
9 G input Active-low output enable; when held high all drain outputs are turned off and the output buffers are forced low, and it can be used for global PWM dimming.
10 GND power_in Power ground; all voltages are referenced to GND and the DMOS sources are internally connected to GND.
11 GND power_in Power ground; all voltages are referenced to GND and the DMOS sources are internally connected to GND.
12 RCK input Register clock; the rising edge transfers the shift register contents to the storage register, and data is valid for read and write only while RCK is low.
13 SRCK input Shift register clock; data on SER IN is shifted in on the rising edge, with a minimum pulse width of 40 ns.
14 DRAIN4 output Low-side open-drain power DMOS output rated for 50 V drain-to-source and 150 mA continuous sink current, with typical 500 mA current limit at TC = 25°C.
15 DRAIN5 output Low-side open-drain power DMOS output rated for 50 V drain-to-source and 150 mA continuous sink current, with typical 500 mA current limit at TC = 25°C.
16 DRAIN6 output Low-side open-drain power DMOS output rated for 50 V drain-to-source and 150 mA continuous sink current, with typical 500 mA current limit at TC = 25°C.
17 DRAIN7 output Low-side open-drain power DMOS output rated for 50 V drain-to-source and 150 mA continuous sink current, with typical 500 mA current limit at TC = 25°C.
18 SER OUT output Serial data output from the shift register, used to daisy-chain to the SER IN pin of the next device.
19 GND power_in Power ground; all voltages are referenced to GND and the DMOS sources are internally connected to GND.
20 NC unconnected No internal connection; leave this pin unconnected.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: TPIC6B595N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: PDIP-20 (KiCad packages3D, STEP)
  • 3D model files: tpic6b595n-etched.step / tpic6b595n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpic6b595n.step / tpic6b595n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 775d4a56485fc3c2, retrieved 2026-10-13, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF