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TPIC6B273DWR

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by adom

Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

markdown

TPIC6B273DWR

Texas Instruments · Latches · SOIC-20-300mil

TPIC6B273DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Asynchronous clear input; when low all DMOS outputs turn off; when high enables data latching on positive clock edge.
2 D1 input Data input 1 with 20 ns setup and hold time; latches to DRAIN1 on positive CLK edge.
3 D2 input Data input 2 with 20 ns setup and hold time; latches to DRAIN2 on positive CLK edge.
4 DRAIN1 output Open-drain power DMOS output 1; 50 V maximum drain-to-source voltage, 150 mA continuous sink current, 500 mA typical current-limit rating.
5 DRAIN2 output Open-drain power DMOS output 2; 50 V maximum drain-to-source voltage, 150 mA continuous sink current, 500 mA typical current-limit rating.
6 DRAIN3 output Open-drain power DMOS output 3; 50 V maximum drain-to-source voltage, 150 mA continuous sink current, 500 mA typical current-limit rating.
7 DRAIN4 output Open-drain power DMOS output 4; 50 V maximum drain-to-source voltage, 150 mA continuous sink current, 500 mA typical current-limit rating.
8 D3 input Data input 3 with 20 ns setup and hold time; latches to DRAIN3 on positive CLK edge.
9 D4 input Data input 4 with 20 ns setup and hold time; latches to DRAIN4 on positive CLK edge.
10 GND power_in Ground; source terminal for all power DMOS outputs and negative terminal of logic supply.
11 CLK input Clock input; positive-edge triggered; latches D inputs to DRAIN outputs when CLR is high.
12 D5 input Data input 5 with 20 ns setup and hold time; latches to DRAIN5 on positive CLK edge.
13 D6 input Data input 6 with 20 ns setup and hold time; latches to DRAIN6 on positive CLK edge.
14 DRAIN5 output Open-drain power DMOS output 5; 50 V maximum drain-to-source voltage, 150 mA continuous sink current, 500 mA typical current-limit rating.
15 DRAIN6 output Open-drain power DMOS output 6; 50 V maximum drain-to-source voltage, 150 mA continuous sink current, 500 mA typical current-limit rating.
16 DRAIN7 output Open-drain power DMOS output 7; 50 V maximum drain-to-source voltage, 150 mA continuous sink current, 500 mA typical current-limit rating.
17 DRAIN8 output Open-drain power DMOS output 8; 50 V maximum drain-to-source voltage, 150 mA continuous sink current, 500 mA typical current-limit rating.
18 D7 input Data input 7 with 20 ns setup and hold time; latches to DRAIN7 on positive CLK edge.
19 D8 input Data input 8 with 20 ns setup and hold time; latches to DRAIN8 on positive CLK edge.
20 VCC power_in Logic supply voltage; recommended operating range 4.5 V to 5.5 V per page 4 operating conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: TPIC6B273DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: tpic6b273dwr-etched.step / tpic6b273dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpic6b273dwr.step / tpic6b273dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 80e98b6b048a5e12, retrieved 2026-09-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF