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TPIC6B259N

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Texas Instruments Latches, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icstpic6b259nfactory-2.0.0extractor-text

Verified TPIC6B259N

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPIC6B259N · PDIP-20 · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 20-page datasheet
  • ✓distributor: lcsc C1547789, digikey 2156-TPIC6B259N-ND, mouser 595-TPIC6B259N
  • ✓family: DIP-20_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-96lgzvm_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tpic6b259n.kicad_sym✓ tpic6b259n.kicad_mod✓ tpic6b259n.step
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Ray Publish 0.1.0 9c4190f 7h ago

TPIC6B259N

Texas Instruments · Latches · PDIP-20

TPIC6B259N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection.
2 VCC power_in Logic supply voltage, 4.5 V to 5.5 V recommended (7 V absolute maximum).
3 S0 input Latch select address input bit 0 (LSB), which with S1 and S2 selects the addressed drain output.
4 DRAIN0 output Open-drain DMOS output 0 rated 50 V with 150 mA continuous sink current.
5 DRAIN1 output Open-drain DMOS output 1 rated 50 V with 150 mA continuous sink current.
6 DRAIN2 output Open-drain DMOS output 2 rated 50 V with 150 mA continuous sink current.
7 DRAIN3 output Open-drain DMOS output 3 rated 50 V with 150 mA continuous sink current.
8 S1 input Latch select address input bit 1, which with S0 and S2 selects the addressed drain output.
9 GND power_in Ground and power DMOS source connection, internally common with the other GND pins.
10 GND power_in Ground and power DMOS source connection, internally common with the other GND pins.
11 GND power_in Ground and power DMOS source connection, internally common with the other GND pins.
12 S2 input Latch select address input bit 2 (MSB), which with S0 and S1 selects the addressed drain output.
13 G input Enable input, active low, which should be held high while the address lines are changing to avoid writing erroneous data.
14 DRAIN4 output Open-drain DMOS output 4 rated 50 V with 150 mA continuous sink current.
15 DRAIN5 output Open-drain DMOS output 5 rated 50 V with 150 mA continuous sink current.
16 DRAIN6 output Open-drain DMOS output 6 rated 50 V with 150 mA continuous sink current.
17 DRAIN7 output Open-drain DMOS output 7 rated 50 V with 150 mA continuous sink current.
18 D input Data input written into the addressed latch; a high level turns the addressed DMOS output on (sinking).
19 CLR input Clear input, active low, which turns all DMOS outputs off regardless of address and data inputs.
20 NC unconnected No internal connection.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Logic supply voltage VCC 4.5 5.5 V 5
High-level input voltage VIH 0.85 VCC 5
Low-level input voltage VIL 0.15 VCC 5
Pulsed drain output current ID -500 500 mA TC = 25°C, VCC = 5 V 5
Setup time, D high before G↑ tsu 20 ns see Figure 2 5
Hold time, D high after G↑ th 20 ns see Figure 2 5
Pulse duration tw 40 ns see Figure 2 5
Operating case temperature TC -40 125 °C 5
Drain-to-source breakdown voltage V(BR)DSX 50 V ID = 1 mA 5
Source-to-drain diode forward voltage VSD 0.85 1 V IF = 100 mA 5
High-level input current IIH 1 µA VCC = 5.5 V, VI = VCC 5
Low-level input current IIL -1 µA VCC = 5.5 V, VI = 0 5
Logic supply current, outputs off ICC 20 100 µA VCC = 5.5 V, all outputs off 5
Logic supply current, outputs on ICC 150 300 µA VCC = 5.5 V, all outputs on 5
Nominal current IN 90 mA VDS(on) = 0.5 V, IN = ID, TC = 85°C 5
Off-state drain current IDSX 0.1 5 µA VDS = 40 V, VCC = 5.5 V 5
Off-state drain current, 125°C IDSX 0.15 8 µA VDS = 40 V, VCC = 5.5 V, TC = 125°C 5
Static drain-to-source on-state resistance rDS(on) 4.2 5.7 Ω ID = 100 mA, VCC = 4.5 V 5
Static drain-to-source on-state resistance, 125°C rDS(on) 6.8 9.5 Ω ID = 100 mA, TC = 125°C, VCC = 4.5 V 5
Static drain-to-source on-state resistance rDS(on) 5.5 8 Ω ID = 350 mA, VCC = 4.5 V 5
Propagation delay, low-to-high from D tPLH 150 ns CL = 30 pF, ID = 100 mA 5
Propagation delay, high-to-low from D tPHL 90 ns CL = 30 pF, ID = 100 mA 5
Rise time, drain output tr 200 ns CL = 30 pF, ID = 100 mA 5
Fall time, drain output tf 200 ns CL = 30 pF, ID = 100 mA 5
Reverse-recovery-current rise time ta 100 ns IF = 100 mA, di/dt = 20 A/µs 5
Reverse-recovery time trr 300 ns IF = 100 mA, di/dt = 20 A/µs 5
Thermal resistance junction-to-ambient, N package RθJA 95 °C/W All 8 outputs with equal power 6
Logic supply voltage VCC 7 V 4
Logic input voltage range VI -0.3 7 V 4
Power DMOS drain-to-source voltage VDS 50 V 4
Continuous source-to-drain diode anode current 500 mA 4
Pulsed source-to-drain diode anode current 1 A Pulse duration ≤ 100 µs, duty cycle ≤ 2% 4
Pulsed drain current, each output ID 500 mA all outputs on, TC = 25°C 4
Continuous drain current, each output ID 150 mA all outputs on, TC = 25°C 4
Peak drain current single output IDM 500 mA TC = 25°C 4
Single-pulse avalanche energy EAS 30 mJ see Figure 4 4
Avalanche current IAS 500 mA 4
Operating virtual junction temperature TJ -40 150 °C 4
Operating case temperature TC -40 125 °C 4
Storage temperature Tstg -65 150 °C 4
Lead temperature 260 °C 1,6 mm from case for 10 seconds 4
Continuous total dissipation, N package 1050 mW TC ≤ 25°C, derate 10.5 mW/°C above 25°C 4

CAD (KiCad official)

  • Symbol: TPIC6B259N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: PDIP-20 (KiCad packages3D, STEP)
  • 3D model files: tpic6b259n-etched.step / tpic6b259n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpic6b259n.step / tpic6b259n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 24fed3b94a80b343, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF