TPIC6273N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CLR	input	Asynchronous clear input that the datasheet says is provided to turn all eight DMOS-transistor outputs off.
2	D1	input	Data input for channel 1, transferred to DRAIN1 on the positive-going CLK edge when the 10 ns setup and 15 ns hold times are met.
3	D2	input	Data input for channel 2, transferred to DRAIN2 on the positive-going CLK edge when the 10 ns setup and 15 ns hold times are met.
4	DRAIN1	output	Open-drain power DMOS output of channel 1, rated for 250 mA continuous and 1.5 A pulsed drain current with a 45 V drain-source breakdown.
5	DRAIN2	output	Open-drain power DMOS output of channel 2, rated for 250 mA continuous and 1.5 A pulsed drain current with a 45 V drain-source breakdown.
6	DRAIN3	output	Open-drain power DMOS output of channel 3, rated for 250 mA continuous and 1.5 A pulsed drain current with a 45 V drain-source breakdown.
7	DRAIN4	output	Open-drain power DMOS output of channel 4, rated for 250 mA continuous and 1.5 A pulsed drain current with a 45 V drain-source breakdown.
8	D3	input	Data input for channel 3, transferred to DRAIN3 on the positive-going CLK edge when the 10 ns setup and 15 ns hold times are met.
9	D4	input	Data input for channel 4, transferred to DRAIN4 on the positive-going CLK edge when the 10 ns setup and 15 ns hold times are met.
10	GND	power_in	Ground reference for all voltages; each power DMOS source is internally connected to GND.
11	CLK	input	Clock input whose positive-going edge latches the D inputs to the DRAIN outputs, with a minimum pulse duration of 25 ns.
12	D5	input	Data input for channel 5, transferred to DRAIN5 on the positive-going CLK edge when the 10 ns setup and 15 ns hold times are met.
13	D6	input	Data input for channel 6, transferred to DRAIN6 on the positive-going CLK edge when the 10 ns setup and 15 ns hold times are met.
14	DRAIN5	output	Open-drain power DMOS output of channel 5, rated for 250 mA continuous and 1.5 A pulsed drain current with a 45 V drain-source breakdown.
15	DRAIN6	output	Open-drain power DMOS output of channel 6, rated for 250 mA continuous and 1.5 A pulsed drain current with a 45 V drain-source breakdown.
16	DRAIN7	output	Open-drain power DMOS output of channel 7, rated for 250 mA continuous and 1.5 A pulsed drain current with a 45 V drain-source breakdown.
17	DRAIN8	output	Open-drain power DMOS output of channel 8, rated for 250 mA continuous and 1.5 A pulsed drain current with a 45 V drain-source breakdown.
18	D7	input	Data input for channel 7, transferred to DRAIN7 on the positive-going CLK edge when the 10 ns setup and 15 ns hold times are met.
19	D8	input	Data input for channel 8, transferred to DRAIN8 on the positive-going CLK edge when the 10 ns setup and 15 ns hold times are met.
20	VCC	power_in	Logic supply voltage, recommended 4.5 V to 5.5 V, with an absolute maximum of 7 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	PDIP-20
Category	Logic ICs
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Logic supply voltage	VCC	4.5		5.5	V		4
Pulsed drain output current		-1.8		1.5	A	TC = 25°C, VCC = 5 V	4
Setup time, D high before CLK↑	tsu	10			ns	see Figure 2	4
Hold time, D high after CLK↑	th	15			ns	see Figure 2	4
Pulse duration	tw	25			ns	see Figure 2	4
Operating case temperature	TC	-40		125	°C		4
Drain-source breakdown voltage	V(BR)DSX	45			V	ID = 1 mA	4
Source-drain diode forward voltage	VSD		0.85	1	V	IF = 250 mA, See Note 3	4
High-level input current	IIH			1	µA	VCC = 5.5 V, VI = VCC	4
Low-level input current	IIL			-1	µA	VCC = 5.5 V, VI = 0	4
Logic supply current	ICC		15	100	µA	IO = 0, All inputs low	4
Nominal current	IN	250			mA	VDS(on) = 0.5 V, IN = ID, TC = 85°C; See Notes 5, 6, and 7	4
Off-state drain current	IDSX		0.05	1	µA	VDS = 40 V	4
Off-state drain current at TC = 125°C	IDSX		0.15	5	µA	VDS = 40 V, TC = 125°C	4
Static drain-source on-state resistance	rDS(on)		1.3	2	Ω	ID = 250 mA, VCC = 4.5 V	4
Static drain-source on-state resistance at TC = 125°C	rDS(on)		2	3.2	Ω	ID = 250 mA, TC = 125°C, VCC = 4.5 V; See Notes 5 and 6 and Figures 8 and 9	4
Propagation delay time, low-to-high-level output from CLK	tPLH			625	ns	CL = 30 pF, ID = 250 mA, See Figures 1, 2, and 10	4
Propagation delay time, high-to-low-level output from CLK	tPHL			150	ns	CL = 30 pF, ID = 250 mA, See Figures 1, 2, and 10	4
Rise time, drain output	tr			675	ns	CL = 30 pF, ID = 250 mA, See Figures 1, 2, and 10	4
Fall time, drain output	tf			400	ns	CL = 30 pF, ID = 250 mA, See Figures 1, 2, and 10	4
Reverse-recovery-current rise time	ta			100	ns	IF = 250 mA, di/dt = 20 A/µs, See Notes 5 and 6 and Figure 3	4
Reverse-recovery time	trr			300	ns	IF = 250 mA, di/dt = 20 A/µs, See Notes 5 and 6 and Figure 3	4
Logic supply voltage (absolute maximum)	VCC			7	V		3
Logic input voltage range	VI	-0.3		7	V		3
Power DMOS drain-to-source voltage	VDS			45	V	see Note 2	3
Continuous source-drain diode anode current				1	A		3
Pulsed source-drain diode anode current				2	A		3
Pulsed drain current, each output, all outputs on	IDn			750	mA	TA = 25°C, see Note 3	3
Continuous drain current, each output, all outputs on	IDn			250	mA	TA = 25°C	3
Peak drain current single output	IDM			2	A	TA = 25°C, see Note 3	3
Single-pulse avalanche energy	EAS			75	mJ	see Figure 4	3
Avalanche current	IAS			1	A	see Note 4	3
Operating virtual junction temperature range	TJ	-40		150	°C		3
Storage temperature range	Tstg	-65		150	°C		3
Lead temperature				260	°C	1.6 mm (1/16 inch) from case for 10 seconds	3
Continuous total power dissipation, N package				1150	mW	TA ≤ 25°C	3
Continuous total power dissipation, N package				230	mW	TA = 125°C	3
Thermal resistance, junction-to-ambient, N package	RθJA			108	°C/W	All 8 outputs with equal power	4

CAD (KiCad official)

Symbol: TPIC6273N
Footprint: Package_DIP:DIP-20_W7.62mm
3D model: PDIP-20 (KiCad packages3D, STEP)
3D model files: tpic6273n-etched.step / tpic6273n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpic6273n.step / tpic6273n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (18 pp, sha256 1b9dd1de09932ea8, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TPIC6273N

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