component
TPIC6273DWR
Public Made by Adomby adom
Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# TPIC6273DWR++**Texas Instruments** · Latches · SOIC-20-300mil++TPIC6273DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLR | input | Asynchronous clear input that turns all eight DMOS outputs off; D data is transferred to the outputs only on the CLK rising edge while CLR is high. |+| 2 | D1 | input | Data input for channel 1, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC. |+| 3 | D2 | input | Data input for channel 2, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC. |+| 4 | DRAIN1 | output | Open-drain power DMOS output of channel 1, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage. |+| 5 | DRAIN2 | output | Open-drain power DMOS output of channel 2, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage. |+| 6 | DRAIN3 | output | Open-drain power DMOS output of channel 3, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage. |+| 7 | DRAIN4 | output | Open-drain power DMOS output of channel 4, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage. |+| 8 | D3 | input | Data input for channel 3, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC. |+| 9 | D4 | input | Data input for channel 4, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC. |+| 10 | GND | power_in | Ground reference for all voltages; the DMOS sources are internally connected to GND. |+| 11 | CLK | input | Clock input; outputs update on the positive-going edge, and the D inputs have no effect while CLK is held high or low. |+| 12 | D5 | input | Data input for channel 5, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC. |+| 13 | D6 | input | Data input for channel 6, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC. |+| 14 | DRAIN5 | output | Open-drain power DMOS output of channel 5, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage. |+| 15 | DRAIN6 | output | Open-drain power DMOS output of channel 6, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage. |+| 16 | DRAIN7 | output | Open-drain power DMOS output of channel 7, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage. |+| 17 | DRAIN8 | output | Open-drain power DMOS output of channel 8, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage. |+| 18 | D7 | input | Data input for channel 7, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC. |+| 19 | D8 | input | Data input for channel 8, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC. |+| 20 | VCC | power_in | Logic supply voltage, recommended 4.5 V to 5.5 V; absolute maximum 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | Logic ICs |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `TPIC6273DWR`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `tpic6273dwr-etched.step` / `tpic6273dwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpic6273dwr.step` / `tpic6273dwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tpic6273) (18 pp, sha256 `176bae47b01b4e8c`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tpic6273dwr-datasheet.pdf)
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D data is transferred to the outputs only on the CLK rising edge while CLR is high."+ },+ {+ "number": "2",+ "name": "D1",+ "type": "input",+ "description": "Data input for channel 1, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC."+ },+ {+ "number": "3",+ "name": "D2",+ "type": "input",+ "description": "Data input for channel 2, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC."+ },+ {+ "number": "4",+ "name": "DRAIN1",+ "type": "output",+ "description": "Open-drain power DMOS output of channel 1, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage."+ },+ {+ "number": "5",+ "name": "DRAIN2",+ "type": "output",+ "description": "Open-drain power DMOS output of channel 2, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage."+ },+ {+ "number": "6",+ "name": "DRAIN3",+ "type": "output",+ "description": "Open-drain power DMOS output of channel 3, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage."+ },+ {+ "number": "7",+ "name": "DRAIN4",+ "type": "output",+ "description": "Open-drain power DMOS output of channel 4, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage."+ },+ {+ "number": "8",+ "name": "D3",+ "type": "input",+ "description": "Data input for channel 3, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC."+ },+ {+ "number": "9",+ "name": "D4",+ "type": "input",+ "description": "Data input for channel 4, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for all voltages; the DMOS sources are internally connected to GND."+ },+ {+ "number": "11",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; outputs update on the positive-going edge, and the D inputs have no effect while CLK is held high or low."+ },+ {+ "number": "12",+ "name": "D5",+ "type": "input",+ "description": "Data input for channel 5, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC."+ },+ {+ "number": "13",+ "name": "D6",+ "type": "input",+ "description": "Data input for channel 6, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC."+ },+ {+ "number": "14",+ "name": "DRAIN5",+ "type": "output",+ "description": "Open-drain power DMOS output of channel 5, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage."+ },+ {+ "number": "15",+ "name": "DRAIN6",+ "type": "output",+ "description": "Open-drain power DMOS output of channel 6, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage."+ },+ {+ "number": "16",+ "name": "DRAIN7",+ "type": "output",+ "description": "Open-drain power DMOS output of channel 7, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage."+ },+ {+ "number": "17",+ "name": "DRAIN8",+ "type": "output",+ "description": "Open-drain power DMOS output of channel 8, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage."+ },+ {+ "number": "18",+ "name": "D7",+ "type": "input",+ "description": "Data input for channel 7, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC."+ },+ {+ "number": "19",+ "name": "D8",+ "type": "input",+ "description": "Data input for channel 8, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Logic supply voltage, recommended 4.5 V to 5.5 V; absolute maximum 7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pinout comes from the DW (SOIC-20) top-view drawing on page 1. The package addendum on page 9 li; The datasheet's function table is garbled in the text extraction, so the CLR polarity is described o"+ ],+ "pages_sent": 18,+ "cost_usd": 0.0837,+ "at": "2026-10-08T16:06:37"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tpic6273",+ "pages": 18,+ "sha256": "176bae47b01b4e8c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tpic6273dwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "59a10b341e6972b31d81802a048060326da627d8b92dcf4263064f4f62ec808e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tpic6273dwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "092b44fa013cd624b61c9af348f617af6e649b0129c0406db0355af3b418a915",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}