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TPIC6273DWR

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Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPIC6273DWR

Texas Instruments · Latches · SOIC-20-300mil

TPIC6273DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Asynchronous clear input that turns all eight DMOS outputs off; D data is transferred to the outputs only on the CLK rising edge while CLR is high.
2 D1 input Data input for channel 1, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC.
3 D2 input Data input for channel 2, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC.
4 DRAIN1 output Open-drain power DMOS output of channel 1, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage.
5 DRAIN2 output Open-drain power DMOS output of channel 2, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage.
6 DRAIN3 output Open-drain power DMOS output of channel 3, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage.
7 DRAIN4 output Open-drain power DMOS output of channel 4, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage.
8 D3 input Data input for channel 3, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC.
9 D4 input Data input for channel 4, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC.
10 GND power_in Ground reference for all voltages; the DMOS sources are internally connected to GND.
11 CLK input Clock input; outputs update on the positive-going edge, and the D inputs have no effect while CLK is held high or low.
12 D5 input Data input for channel 5, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC.
13 D6 input Data input for channel 6, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC.
14 DRAIN5 output Open-drain power DMOS output of channel 5, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage.
15 DRAIN6 output Open-drain power DMOS output of channel 6, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage.
16 DRAIN7 output Open-drain power DMOS output of channel 7, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage.
17 DRAIN8 output Open-drain power DMOS output of channel 8, rated for 250 mA continuous drain current and 45 V drain-source breakdown voltage.
18 D7 input Data input for channel 7, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC.
19 D8 input Data input for channel 8, sampled on the positive-going CLK edge; input thresholds are VIH of at least 0.85 VCC and VIL of at most 0.15 VCC.
20 VCC power_in Logic supply voltage, recommended 4.5 V to 5.5 V; absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic ICs
Pins 20

CAD (KiCad official)

  • Symbol: TPIC6273DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: tpic6273dwr-etched.step / tpic6273dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpic6273dwr.step / tpic6273dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 176bae47b01b4e8c, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF