component
TPIC44L01DBR
Public Made by Adomby adom
Texas Instruments Gate Drivers, SSOP-24-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 18d ago |
| viewers | 18d ago |
| package.json | 18d ago |
| page.json | 18d ago |
| README.md | 18d ago |
| tpic44l01dbr-etched.glb | 18d ago |
| tpic44l01dbr-etched.step | 18d ago |
| tpic44l01dbr-hero.glb | 18d ago |
| tpic44l01dbr-hero.overlay.json | 18d ago |
| tpic44l01dbr.glb | 18d ago |
| tpic44l01dbr.kicad_mod | 18d ago |
| tpic44l01dbr.kicad_sym | 18d ago |
| tpic44l01dbr.lbr | 18d ago |
| tpic44l01dbr.step | 18d ago |
TPIC44L01DBR
Texas Instruments · Gate Drivers · SSOP-24-208mil
TPIC44L01DBR from Texas Instruments, in a SSOP-24-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FLT | output | Open-drain logic-level real-time fault flag for shorted-load, open-load, over-battery and under-battery faults, which requires an external pullup resistor. |
| 2 | VCOMPEN | input | Fault reference select: connecting it to GND selects the internal fault reference and connecting it to VCC selects the external VCOMP reference. |
| 3 | VCOMP | input | External fault reference voltage input for shorted-load and open-load detection, used only when VCOMPEN is connected to VCC. |
| 4 | IN0 | input | Parallel gate control input for channel 0 with CMOS-compatible hysteresis, where a 1 turns GATE0 on and a 0 turns it off. |
| 5 | IN1 | input | Parallel gate control input for channel 1 with CMOS-compatible hysteresis, where a 1 turns GATE1 on and a 0 turns it off. |
| 6 | IN2 | input | Parallel gate control input for channel 2 with CMOS-compatible hysteresis, where a 1 turns GATE2 on and a 0 turns it off. |
| 7 | IN3 | input | Parallel gate control input for channel 3 with CMOS-compatible hysteresis, where a 1 turns GATE3 on and a 0 turns it off. |
| 8 | CS | input | Chip select: a high-to-low transition enables SDO, latches fault data and refreshes FLT, and a low-to-high transition latches serial data into the output control register; it has a pullup resistor. |
| 9 | SDO | tri_state | Serial data output, a 3-state output that transfers fault data and passes serial input data to the next stage, and is high-impedance while CS is high. |
| 10 | SDI | input | Serial data input clocked into the serial register on SCLK, where a 1 commands the gate output on and a 0 turns it off. |
| 11 | SCLK | input | Serial clock that shifts data into SDI and clocks serial fault data out of SDO on the falling edge. |
| 12 | VCC | power_in | Logic supply voltage, recommended 4.5 V to 5.5 V with 5 V nominal. |
| 13 | GND | power_in | Ground and substrate reference for all voltages on the device. |
| 14 | DRAIN3 | input | FET drain input for channel 3 used for open-load and shorted-load fault detection and inductive transient protection. |
| 15 | GATE3 | output | Gate drive output for the channel 3 external FET, derived from VBAT and clamped to protect the FET VGS rating. |
| 16 | DRAIN2 | input | FET drain input for channel 2 used for open-load and shorted-load fault detection and inductive transient protection. |
| 17 | GATE2 | output | Gate drive output for the channel 2 external FET, derived from VBAT and clamped to protect the FET VGS rating. |
| 18 | GATE1 | output | Gate drive output for the channel 1 external FET, derived from VBAT and clamped to protect the FET VGS rating. |
| 19 | DRAIN1 | input | FET drain input for channel 1 used for open-load and shorted-load fault detection and inductive transient protection. |
| 20 | GATE0 | output | Gate drive output for the channel 0 external FET, derived from VBAT and clamped to protect the FET VGS rating. |
| 21 | DRAIN0 | input | FET drain input for channel 0 used for open-load and shorted-load fault detection and inductive transient protection. |
| 22 | RESET | input | Active-low reset: a high-to-low transition clears all registers and flags, turns the gate outputs off and clears FLT, and it has a pullup resistor. |
| 23 | N/C | unconnected | Not connected; the pin is shown as N/C in the pin diagram and has no function listed. |
| 24 | VBAT | power_in | Battery supply voltage, recommended 8 V to 24 V, with an absolute maximum of 60 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SSOP-24-208mil |
| Category | Motor Driver ICs |
| Pins | 24 |
CAD (KiCad official)
- Symbol:
TPIC44L01DBR - Footprint:
Package_SO:SSOP-24_5.3x8.2mm_P0.65mm - 3D model: SSOP-24-208mil (KiCad packages3D, STEP)
- 3D model files:
tpic44l01dbr-etched.step/tpic44l01dbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpic44l01dbr.step/tpic44l01dbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (24 pp, sha256
0a0f55fd5c38c81c, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).