component
TPH5900CNH
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TOSHIBA MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPH5900CNH
TOSHIBA · MOSFETs · SOP-8
TPH5900CNH from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Source | passive | Source terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 2 | Source | passive | Source terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 3 | Source | passive | Source terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 4 | Gate | input | Gate terminal of the MOSFET; the datasheet gives the gate-source voltage rating VGSS as ±20 V. |
| 5 | Drain | passive | Drain terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 6 | Drain | passive | Drain terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 7 | Drain | passive | Drain terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 8 | Drain | passive | Drain terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDSS | 150 | V | 1 | |||
| Gate-source voltage | VGSS | -20 | 20 | V | 1 | ||
| Drain current (DC), silicon limit | ID | 18 | A | Silicon limit (Note 1, 2) | 1 | ||
| Drain current (DC), continuous | ID | 9 | A | Continuous (Note 1) | 1 | ||
| Drain current (pulsed) | IDP | 35 | A | t = 1 ms | 1 | ||
| Power dissipation | PD | 42 | W | Tc = 25 | 1 | ||
| Power dissipation (glass-epoxy board a) | PD | 2.8 | W | t = 10 s (Note 3, Fig. 5.1) | 1 | ||
| Power dissipation (glass-epoxy board b) | PD | 1.6 | W | t = 10 s (Note 4, Fig. 5.2) | 1 | ||
| Single-pulse avalanche energy | EAS | 36 | mJ | Note 5: VDD = 60 V, Tch = 25, L = 630 µH, IAR = 9.0 A | 1 | ||
| Avalanche current | IAR | 9 | A | Note 5 | 1 | ||
| Channel temperature | Tch | 150 | °C | 1 | |||
| Storage temperature | Tstg | -55 | 150 | °C | 1 | ||
| Channel-to-case thermal resistance | Rth(ch-c) | 2.97 | °C/W | Tc = 25 | 2 | ||
| Channel-to-ambient thermal resistance (board a) | Rth(ch-a) | 44.6 | °C/W | t = 10 s (Note 3) | 2 | ||
| Channel-to-ambient thermal resistance (board b) | Rth(ch-a) | 78.1 | °C/W | t = 10 s (Note 4) | 2 | ||
| Gate leakage current | IGSS | -0.1 | 0.1 | µA | VGS = ±20 V, VDS = 0 V | 3 | |
| Drain cut-off current | IDSS | 10 | µA | VDS = 150 V, VGS = 0 V | 3 | ||
| Drain-source breakdown voltage | V(BR)DSS | 150 | V | ID = 10 mA, VGS = 0 V | 3 | ||
| Drain-source breakdown voltage (VGS = -20 V) | V(BR)DSX | 105 | V | ID = 10 mA, VGS = -20 V | 3 | ||
| Gate threshold voltage | Vth | 2 | 4 | V | VDS = 10 V, ID = 0.2 mA | 3 | |
| Drain-source on-resistance | RDS(ON) | 50 | 59 | mΩ | VGS = 10 V, ID = 4.5 A | 3 | |
| Input capacitance | Ciss | 460 | 600 | pF | VDS = 75 V, VGS = 0 V, f = 1 MHz | 3 | |
| Reverse transfer capacitance | Crss | 3 | 50 | pF | 3 | ||
| Gate resistance | rg | 4 | 6 | Ω | 3 | ||
| Reverse drain current (pulsed) | IDRP | 35 | A | 3 | |||
| Diode forward voltage | VDSF | -1.2 | V | IDR = 9.0 A, VGS = 0 V | 3 |
CAD (KiCad official)
- Symbol:
TPH5900CNH - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
tph5900cnh-etched.step/tph5900cnh-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tph5900cnh.step/tph5900cnh.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (9 pp, sha256
5947d79faab7a8b4, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPH5900CNH
**TOSHIBA** · MOSFETs · SOP-8
TPH5900CNH from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Source | passive | Source terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 2 | Source | passive | Source terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 3 | Source | passive | Source terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 4 | Gate | input | Gate terminal of the MOSFET; the datasheet gives the gate-source voltage rating VGSS as ±20 V. |
| 5 | Drain | passive | Drain terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 6 | Drain | passive | Drain terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 7 | Drain | passive | Drain terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
| 8 | Drain | passive | Drain terminal of the N-channel MOSFET; the datasheet gives the drain-source voltage rating VDSS as 150 V for the device. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDSS | | | 150 | V | | 1 |
| Gate-source voltage | VGSS | -20 | | 20 | V | | 1 |
| Drain current (DC), silicon limit | ID | | | 18 | A | Silicon limit (Note 1, 2) | 1 |
| Drain current (DC), continuous | ID | | | 9 | A | Continuous (Note 1) | 1 |
| Drain current (pulsed) | IDP | | | 35 | A | t = 1 ms | 1 |
| Power dissipation | PD | | | 42 | W | Tc = 25 | 1 |
| Power dissipation (glass-epoxy board a) | PD | | | 2.8 | W | t = 10 s (Note 3, Fig. 5.1) | 1 |
| Power dissipation (glass-epoxy board b) | PD | | | 1.6 | W | t = 10 s (Note 4, Fig. 5.2) | 1 |
| Single-pulse avalanche energy | EAS | | | 36 | mJ | Note 5: VDD = 60 V, Tch = 25, L = 630 µH, IAR = 9.0 A | 1 |
| Avalanche current | IAR | | | 9 | A | Note 5 | 1 |
| Channel temperature | Tch | | | 150 | °C | | 1 |
| Storage temperature | Tstg | -55 | | 150 | °C | | 1 |
| Channel-to-case thermal resistance | Rth(ch-c) | | | 2.97 | °C/W | Tc = 25 | 2 |
| Channel-to-ambient thermal resistance (board a) | Rth(ch-a) | | | 44.6 | °C/W | t = 10 s (Note 3) | 2 |
| Channel-to-ambient thermal resistance (board b) | Rth(ch-a) | | | 78.1 | °C/W | t = 10 s (Note 4) | 2 |
| Gate leakage current | IGSS | -0.1 | | 0.1 | µA | VGS = ±20 V, VDS = 0 V | 3 |
| Drain cut-off current | IDSS | | | 10 | µA | VDS = 150 V, VGS = 0 V | 3 |
| Drain-source breakdown voltage | V(BR)DSS | 150 | | | V | ID = 10 mA, VGS = 0 V | 3 |
| Drain-source breakdown voltage (VGS = -20 V) | V(BR)DSX | 105 | | | V | ID = 10 mA, VGS = -20 V | 3 |
| Gate threshold voltage | Vth | 2 | | 4 | V | VDS = 10 V, ID = 0.2 mA | 3 |
| Drain-source on-resistance | RDS(ON) | | 50 | 59 | mΩ | VGS = 10 V, ID = 4.5 A | 3 |
| Input capacitance | Ciss | | 460 | 600 | pF | VDS = 75 V, VGS = 0 V, f = 1 MHz | 3 |
| Reverse transfer capacitance | Crss | | 3 | 50 | pF | | 3 |
| Gate resistance | rg | | 4 | 6 | Ω | | 3 |
| Reverse drain current (pulsed) | IDRP | | | 35 | A | | 3 |
| Diode forward voltage | VDSF | | | -1.2 | V | IDR = 9.0 A, VGS = 0 V | 3 |
## CAD (KiCad official)
- Symbol: `TPH5900CNH`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `tph5900cnh-etched.step` / `tph5900cnh-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tph5900cnh.step` / `tph5900cnh.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TOSHIBA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8555045786018693120) (9 pp, sha256 `5947d79faab7a8b4`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tph5900cnh-datasheet.pdf)