component
TPH4R10ANL
Public Made by Adomby adom
TOSHIBA MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPH4R10ANL
TOSHIBA · MOSFETs · SOP-8
TPH4R10ANL from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Source | passive | Source terminal of the MOSFET; the datasheet lists pins 1, 2 and 3 as Source, with a drain-source voltage rating of 100 V (VDSS). |
| 2 | Source | passive | Source terminal of the MOSFET; the datasheet lists pins 1, 2 and 3 as Source, with a drain-source voltage rating of 100 V (VDSS). |
| 3 | Source | passive | Source terminal of the MOSFET; the datasheet lists pins 1, 2 and 3 as Source, with a drain-source voltage rating of 100 V (VDSS). |
| 4 | Gate | input | Gate terminal; the gate-source voltage is rated ±20 V (VGSS) and the gate threshold voltage Vth is 1.5 to 2.5 V (VDS = 10 V, ID = 1.0 mA). |
| 5 | Drain | passive | Drain terminal; the drain-source voltage is rated 100 V (VDSS) and the DC drain current is rated 70 A at Tc = 25 °C. |
| 6 | Drain | passive | Drain terminal; the drain-source voltage is rated 100 V (VDSS) and the DC drain current is rated 70 A at Tc = 25 °C. |
| 7 | Drain | passive | Drain terminal; the drain-source voltage is rated 100 V (VDSS) and the DC drain current is rated 70 A at Tc = 25 °C. |
| 8 | Drain | passive | Drain terminal; the drain-source voltage is rated 100 V (VDSS) and the DC drain current is rated 70 A at Tc = 25 °C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOP-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate leakage current | IGSS | -0.1 | 0.1 | µA | VGS = ±20 V, VDS = 0 V | 3 | |
| Drain cut-off current | IDSS | 10 | µA | VDS = 100 V, VGS = 0 V | 3 | ||
| Drain-source breakdown voltage | V(BR)DSS | 100 | V | ID = 10 mA, VGS = 0 V | 3 | ||
| Drain-source breakdown voltage | V(BR)DSX | 65 | V | ID = 10 mA, VGS = -20 V | 3 | ||
| Gate threshold voltage | Vth | 1.5 | 2.5 | V | VDS = 10 V, ID = 1.0 mA | 3 | |
| Drain-source on-resistance | RDS(ON) | 4.1 | 6.6 | mΩ | VGS = 4.5 V, ID = 20 A | 3 | |
| Drain-source on-resistance | RDS(ON) | 3.3 | 4.1 | mΩ | VGS = 10 V, ID = 35 A | 3 | |
| Input capacitance | Ciss | 4850 | 6300 | pF | VDS = 50 V, VGS = 0 V, f = 1 MHz | 3 | |
| Reverse transfer capacitance | Crss | 29 | 59 | pF | VDS = 50 V, VGS = 0 V, f = 1 MHz | 3 | |
| Gate resistance | rg | 2.1 | 3.2 | Ω | 3 | ||
| Reverse drain current (pulsed) | IDRP | 490 | A | t = 100 µs | 4 | ||
| Diode forward voltage | VDSF | -1.2 | V | IDR = 70 A, VGS = 0 V | 4 | ||
| Drain current (DC) | ID | 70 | A | Tc = 25 °C | 2 | ||
| Drain current (DC) silicon limit | ID | 92 | A | Silicon limit | 2 | ||
| Drain current (pulsed) | IDP | 490 | A | t = 100 µs | 2 | ||
| Drain-source voltage | VDSS | 100 | V | 2 | |||
| Gate-source voltage | VGSS | -20 | 20 | V | 2 | ||
| Power dissipation | PD | 67 | W | Tc = 25 °C | 2 | ||
| Power dissipation | PD | 2.5 | W | Note 1, Note 2 | 2 | ||
| Power dissipation | PD | 0.8 | W | Note 1 | 2 | ||
| Single-pulse avalanche energy | EAS | 118 | mJ | Note 5: VDD = 60 V, Tch = 25 °C, L = 26 µH, IAS = 70 A | 2 | ||
| Single-pulse avalanche current | IAS | 70 | A | Note 5: VDD = 60 V, Tch = 25 °C, L = 26 µH | 2 | ||
| Channel temperature | Tch | 150 | °C | Note 1: channel temperature must not exceed 150 °C | 2 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 2 | ||
| Channel-to-case thermal resistance | Rth(ch-c) | 1.86 | °C/W | Tc = 25 °C | 2 | ||
| Channel-to-ambient thermal resistance | Rth(ch-a) | 50 | °C/W | Ta = 25 °C, Note 3 (glass-epoxy board (a)) | 2 | ||
| Channel-to-ambient thermal resistance | Rth(ch-a) | 156 | °C/W | Ta = 25 °C, Note 4 (glass-epoxy board (b)) | 2 |
CAD (KiCad official)
- Symbol:
TPH4R10ANL - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
tph4r10anl-etched.step/tph4r10anl-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tph4r10anl.step/tph4r10anl.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (9 pp, sha256
d10e64bf76926aca, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).