main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers tph1r306pl1: viewers · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago
tph1r306pl1-etched.glb Publish 0.1.0 · Ray 8d ago
tph1r306pl1-etched.step tph1r306pl1: factory component page (tier=mfr) · Ray 8d ago
tph1r306pl1-hero.glb tph1r306pl1: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
tph1r306pl1-hero.overlay.json Publish 0.1.0 · Ray 8d ago
tph1r306pl1.glb Publish 0.1.0 · Ray 8d ago
tph1r306pl1.kicad_mod Publish 0.1.0 · Ray 8d ago
tph1r306pl1.kicad_sym Publish 0.1.0 · Ray 8d ago
tph1r306pl1.lbr Publish 0.1.0 · Ray 8d ago
tph1r306pl1.step Publish 0.1.0 · Ray 8d ago

TPH1R306PL1

TOSHIBA · MOSFETs · SOP-8

TPH1R306PL1 from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source pin, tied internally with pins 2 and 3 to the MOSFET source.
2 S passive Source pin, tied internally with pins 1 and 3 to the MOSFET source.
3 S passive Source pin, tied internally with pins 1 and 2 to the MOSFET source.
4 G input Gate pin with VGSS rating of ±20 V and threshold Vth of 1.5 to 2.5 V (VDS = 10 V, ID = 1.0 mA).
5 D passive Drain pin, tied internally with pins 6, 7 and 8; VDSS is 60 V.
6 D passive Drain pin, tied internally with pins 5, 7 and 8; VDSS is 60 V.
7 D passive Drain pin, tied internally with pins 5, 6 and 8; VDSS is 60 V.
8 D passive Drain pin, tied internally with pins 5, 6 and 7; VDSS is 60 V.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package SOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gate leakage current IGSS -0.1 0.1 µA VGS = ±20 V, VDS = 0 V 3
Drain cut-off current IDSS 10 µA VDS = 60 V, VGS = 0 V 3
Drain-source breakdown voltage V(BR)DSS 60 V ID = 10 mA, VGS = 0 V 3
Drain-source breakdown voltage V(BR)DSX 45 V ID = 10 mA, VGS = -20 V 3
Gate threshold voltage Vth 1.5 2.5 V VDS = 10 V, ID = 1.0 mA 3
Drain-source on-resistance RDS(ON) 1.5 2.3 mΩ VGS = 4.5 V, ID = 42 A 3
Drain-source on-resistance RDS(ON) 1 1.34 mΩ VGS = 10 V, ID = 50 A 3
Gate resistance rg 0.5 1 Ω VDS = 30 V, VGS = 0 V, f = 1 MHz 3
Diode forward voltage VDSF -1.2 V IDR = 100 A, VGS = 0 V 4
Reverse drain current (pulsed) IDRP 500 A t = 100 µs 4
Drain-source voltage VDSS 60 V Ta = 25 °C 2
Gate-source voltage VGSS -20 20 V Ta = 25 °C 2
Drain current (DC) ID 100 A Tc = 25 °C 2
Drain current (DC), silicon limit ID 280 A Tc = 25 °C, Silicon limit 2
Drain current (pulsed) IDP 500 A t = 100 µs 2
Power dissipation PD 210 W Tc = 25 °C 2
Power dissipation PD 3 W Note 3 2
Power dissipation PD 0.96 W Note 4 2
Single-pulse avalanche energy EAS 455 mJ VDD = 48 V, Tch = 25 °C (initial), L = 140 µH, IAS = 50 A 2
Single-pulse avalanche current IAS 50 A 2
Channel temperature Tch 175 °C 2
Storage temperature Tstg -55 175 °C 2
Channel-to-case thermal resistance Rth(ch-c) 0.71 °C/W Tc = 25 °C 2
Channel-to-ambient thermal resistance Rth(ch-a) 50 °C/W Note 3 2
Channel-to-ambient thermal resistance Rth(ch-a) 156 °C/W Note 4 2
Input capacitance Ciss 6250 8100 pF VDS = 30 V, VGS = 0 V, f = 1 MHz 3
Reverse transfer capacitance Crss 80 pF VDS = 30 V, VGS = 0 V, f = 1 MHz 3
Output capacitance Coss 1160 pF VDS = 30 V, VGS = 0 V, f = 1 MHz 3
Total gate charge Qg 91 nC VDD ≈ 30 V, VGS = 10 V, ID = 50 A 3
Gate switch charge QSW 22 nC VDD ≈ 30 V, VGS = 10 V, ID = 50 A 3
Output charge Qoss 77.5 nC VDS = 30 V, VGS = 0 V, f = 1 MHz 3
Reverse recovery time trr 47 ns VR = 30 V, IDR = 25 A, VGS = 0 V, -dIDR/dt = 100 A/µs 4
Reverse recovery charge Qrr 48 nC VR = 30 V, IDR = 25 A, VGS = 0 V, -dIDR/dt = 100 A/µs 4

CAD (KiCad official)

  • Symbol: TPH1R306PL1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tph1r306pl1-etched.step / tph1r306pl1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tph1r306pl1.step / tph1r306pl1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (9 pp, sha256 fbe57280f30f79f1, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF