component
TPH1R306PL
Public Made by Adomby adom
TOSHIBA MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPH1R306PL
TOSHIBA · MOSFETs · SOP-8
TPH1R306PL from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Source | passive | Source terminal; the device is rated VDSS 60 V and VGSS ±20 V. |
| 2 | Source | passive | Source terminal; the device is rated VDSS 60 V and VGSS ±20 V. |
| 3 | Source | passive | Source terminal; the device is rated VDSS 60 V and VGSS ±20 V. |
| 4 | Gate | input | Gate terminal; gate-source voltage is rated ±20 V (VGSS) and gate threshold voltage Vth is 1.5 to 2.5 V. |
| 5 | Drain | passive | Drain terminal; drain-source voltage is rated 60 V (VDSS). |
| 6 | Drain | passive | Drain terminal; drain-source voltage is rated 60 V (VDSS). |
| 7 | Drain | passive | Drain terminal; drain-source voltage is rated 60 V (VDSS). |
| 8 | Drain | passive | Drain terminal; drain-source voltage is rated 60 V (VDSS). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDSS | 60 | V | 2 | |||
| Gate-source voltage | VGSS | -20 | 20 | V | 2 | ||
| Drain current (DC) | ID | 100 | A | Tc = 25 °C | 2 | ||
| Drain current (DC) (silicon limit) | ID | 260 | A | Limited by silicon chip capability | 2 | ||
| Drain current (pulsed) | IDP | 500 | A | t = 100 µs | 2 | ||
| Power dissipation | PD | 170 | W | Tc = 25 °C | 2 | ||
| Power dissipation (glass-epoxy board a) | PD | 3 | W | Device mounted on glass-epoxy board (a), Fig. 5.1 | 2 | ||
| Power dissipation (glass-epoxy board b) | PD | 0.96 | W | Device mounted on glass-epoxy board (b), Fig. 5.2 | 2 | ||
| Single-pulse avalanche energy | EAS | 455 | mJ | VDD = 48 V, Tch = 25 °C (initial), L = 140 µH, IAS = 50 A | 2 | ||
| Single-pulse avalanche current | IAS | 50 | A | VDD = 48 V, Tch = 25 °C (initial), L = 140 µH | 2 | ||
| Channel temperature | Tch | 175 | °C | 2 | |||
| Storage temperature | Tstg | -55 | 175 | °C | 2 | ||
| Channel-to-case thermal resistance | Rth(ch-c) | 0.88 | °C/W | Tc = 25 °C | 2 | ||
| Channel-to-ambient thermal resistance (board a) | Rth(ch-a) | 50 | °C/W | Device mounted on glass-epoxy board (a), Fig. 5.1 | 2 | ||
| Channel-to-ambient thermal resistance (board b) | Rth(ch-a) | 156 | °C/W | Device mounted on glass-epoxy board (b), Fig. 5.2 | 2 | ||
| Gate leakage current | IGSS | -0.1 | 0.1 | µA | VGS = ±20 V, VDS = 0 V | 3 | |
| Drain cut-off current | IDSS | 10 | µA | VDS = 60 V, VGS = 0 V | 3 | ||
| Drain-source breakdown voltage | V(BR)DSS | 60 | V | ID = 10 mA, VGS = 0 V | 3 | ||
| Drain-source breakdown voltage (VGS = -20 V) | V(BR)DSX | 45 | V | ID = 10 mA, VGS = -20 V | 3 | ||
| Gate threshold voltage | Vth | 1.5 | 2.5 | V | VDS = 10 V, ID = 1.0 mA | 3 | |
| Drain-source on-resistance (VGS = 4.5 V) | RDS(ON) | 1.5 | 2.3 | mΩ | VGS = 4.5 V, ID = 42 A | 3 | |
| Drain-source on-resistance (VGS = 10 V) | RDS(ON) | 1 | 1.34 | mΩ | VGS = 10 V, ID = 50 A | 3 | |
| Input capacitance | Ciss | 6250 | 8100 | pF | VDS = 30 V, VGS = 0 V, f = 1 MHz | 3 | |
| Gate resistance | rg | 0.5 | 1 | Ω | 3 | ||
| Reverse drain current (pulsed) | IDRP | 500 | A | t = 100 µs | 4 | ||
| Diode forward voltage | VDSF | -1.2 | V | IDR = 100 A, VGS = 0 V | 4 |
CAD (KiCad official)
- Symbol:
TPH1R306PL - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
tph1r306pl-etched.step/tph1r306pl-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tph1r306pl.step/tph1r306pl.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (10 pp, sha256
a1639a44301ceee0, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPH1R306PL
**TOSHIBA** · MOSFETs · SOP-8
TPH1R306PL from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Source | passive | Source terminal; the device is rated VDSS 60 V and VGSS ±20 V. |
| 2 | Source | passive | Source terminal; the device is rated VDSS 60 V and VGSS ±20 V. |
| 3 | Source | passive | Source terminal; the device is rated VDSS 60 V and VGSS ±20 V. |
| 4 | Gate | input | Gate terminal; gate-source voltage is rated ±20 V (VGSS) and gate threshold voltage Vth is 1.5 to 2.5 V. |
| 5 | Drain | passive | Drain terminal; drain-source voltage is rated 60 V (VDSS). |
| 6 | Drain | passive | Drain terminal; drain-source voltage is rated 60 V (VDSS). |
| 7 | Drain | passive | Drain terminal; drain-source voltage is rated 60 V (VDSS). |
| 8 | Drain | passive | Drain terminal; drain-source voltage is rated 60 V (VDSS). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDSS | | | 60 | V | | 2 |
| Gate-source voltage | VGSS | -20 | | 20 | V | | 2 |
| Drain current (DC) | ID | | | 100 | A | Tc = 25 °C | 2 |
| Drain current (DC) (silicon limit) | ID | | | 260 | A | Limited by silicon chip capability | 2 |
| Drain current (pulsed) | IDP | | | 500 | A | t = 100 µs | 2 |
| Power dissipation | PD | | | 170 | W | Tc = 25 °C | 2 |
| Power dissipation (glass-epoxy board a) | PD | | | 3 | W | Device mounted on glass-epoxy board (a), Fig. 5.1 | 2 |
| Power dissipation (glass-epoxy board b) | PD | | | 0.96 | W | Device mounted on glass-epoxy board (b), Fig. 5.2 | 2 |
| Single-pulse avalanche energy | EAS | | | 455 | mJ | VDD = 48 V, Tch = 25 °C (initial), L = 140 µH, IAS = 50 A | 2 |
| Single-pulse avalanche current | IAS | | | 50 | A | VDD = 48 V, Tch = 25 °C (initial), L = 140 µH | 2 |
| Channel temperature | Tch | | | 175 | °C | | 2 |
| Storage temperature | Tstg | -55 | | 175 | °C | | 2 |
| Channel-to-case thermal resistance | Rth(ch-c) | | | 0.88 | °C/W | Tc = 25 °C | 2 |
| Channel-to-ambient thermal resistance (board a) | Rth(ch-a) | | | 50 | °C/W | Device mounted on glass-epoxy board (a), Fig. 5.1 | 2 |
| Channel-to-ambient thermal resistance (board b) | Rth(ch-a) | | | 156 | °C/W | Device mounted on glass-epoxy board (b), Fig. 5.2 | 2 |
| Gate leakage current | IGSS | -0.1 | | 0.1 | µA | VGS = ±20 V, VDS = 0 V | 3 |
| Drain cut-off current | IDSS | | | 10 | µA | VDS = 60 V, VGS = 0 V | 3 |
| Drain-source breakdown voltage | V(BR)DSS | 60 | | | V | ID = 10 mA, VGS = 0 V | 3 |
| Drain-source breakdown voltage (VGS = -20 V) | V(BR)DSX | 45 | | | V | ID = 10 mA, VGS = -20 V | 3 |
| Gate threshold voltage | Vth | 1.5 | | 2.5 | V | VDS = 10 V, ID = 1.0 mA | 3 |
| Drain-source on-resistance (VGS = 4.5 V) | RDS(ON) | | 1.5 | 2.3 | mΩ | VGS = 4.5 V, ID = 42 A | 3 |
| Drain-source on-resistance (VGS = 10 V) | RDS(ON) | | 1 | 1.34 | mΩ | VGS = 10 V, ID = 50 A | 3 |
| Input capacitance | Ciss | | 6250 | 8100 | pF | VDS = 30 V, VGS = 0 V, f = 1 MHz | 3 |
| Gate resistance | rg | | 0.5 | 1 | Ω | | 3 |
| Reverse drain current (pulsed) | IDRP | | | 500 | A | t = 100 µs | 4 |
| Diode forward voltage | VDSF | | | -1.2 | V | IDR = 100 A, VGS = 0 V | 4 |
## CAD (KiCad official)
- Symbol: `TPH1R306PL`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `tph1r306pl-etched.step` / `tph1r306pl-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tph1r306pl.step` / `tph1r306pl.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TOSHIBA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588912396803325952) (10 pp, sha256 `a1639a44301ceee0`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tph1r306pl-datasheet.pdf)