component
TPDV1240RG
Public Made by Adomby adom
STMicroelectronics Thyristors (SCR)/Modules, TO-3P-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+39@@ -0,0 +1,39 @@+# TPDV1240RG++**STMicroelectronics** · Thyristors (SCR)/Modules · TO-3P-3++TPDV1240RG from STMicroelectronics, in a TO-3P-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A1 | passive | Main terminal A1 of the triac, the reference electrode for A2 voltage and gate; insulated tab is isolated to 2,500 V rms from A1, A2 and gate. |+| 2 | A2 | passive | Main terminal A2 of the triac, blocking up to 1200 V (VDRM/VRRM) for TPDV1240RG and carrying 40 A rms on-state current at Tc = 75 °C. |+| 3 | G | input | Gate trigger terminal, IGT max 200 mA and VGT max 1.5 V (VD = 12 V DC, RL = 33 Ω), with peak gate current 8 A for tp = 20 µs. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | TO-3P-3 |+| Category | Transistors/Thyristors |+| Pins | 3 |++## CAD (KiCad official)++- Symbol: `TPDV1240RG`+- Footprint: `Package_TO_SOT_THT:TO-3P-3_Vertical`+- 3D model: TO-3P-3 (KiCad packages3D, STEP)+- 3D model files: `tpdv1240rg-etched.step` / `tpdv1240rg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpdv1240rg.step` / `tpdv1240rg.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588902952597114880) (8 pp, sha256 `de730887d826ad0f`, retrieved 2026-10-06, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tpdv1240rg-datasheet.pdf)
page.jsonadded+131@@ -0,0 +1,131 @@+{+ "slug": "tpdv1240rg",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics Thyristors (SCR)/Modules, TO-3P-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "transistors-thyristors",+ "tpdv1240rg",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tpdv1240rg.kicad_sym",+ "tpdv1240rg.kicad_mod",+ "tpdv1240rg.glb",+ "tpdv1240rg.step",+ "tpdv1240rg.lbr",+ "docs/hero.png",+ "docs/tpdv1240rg-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tpdv1240rg-hero.glb",+ "tpdv1240rg-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPDV1240RG",+ "manufacturer": "STMicroelectronics",+ "package": "TO-3P-3",+ "pin_count": 3,+ "category": "Transistors/Thyristors",+ "subcategory": "Thyristors (SCR)/Modules",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588902952597114880",+ "parts": {+ "symbol": "tpdv1240rg.kicad_sym",+ "footprint": "tpdv1240rg.kicad_mod",+ "model_3d": "tpdv1240rg-hero.glb",+ "model_3d_plain": "tpdv1240rg.glb",+ "model_3d_step": "tpdv1240rg-etched.step",+ "model_3d_step_plain": "tpdv1240rg.step",+ "lbr": "tpdv1240rg.lbr"+ },+ "distributor_links": {+ "lcsc": 2688496,+ "digikey": "497-3794-5-ND",+ "mouser": "511-TPDV1240"+ },+ "distributor_check": {+ "checked_at": "2026-10-06T04:02:27Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-3794-5-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "511-TPDV1240",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "A1",+ "type": "passive",+ "description": "Main terminal A1 of the triac, the reference electrode for A2 voltage and gate; insulated tab is isolated to 2,500 V rms from A1, A2 and gate."+ },+ {+ "number": "2",+ "name": "A2",+ "type": "passive",+ "description": "Main terminal A2 of the triac, blocking up to 1200 V (VDRM/VRRM) for TPDV1240RG and carrying 40 A rms on-state current at Tc = 75 °C."+ },+ {+ "number": "3",+ "name": "G",+ "type": "input",+ "description": "Gate trigger terminal, IGT max 200 mA and VGT max 1.5 V (VD = 12 V DC, RL = 33 Ω), with peak gate current 8 A for tp = 20 µs."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pin-to-number mapping comes only from the small pictorial on page 1. It labels the leads A1, A2,; The datasheet names the package TOP3 insulated, not TO-3P-3. The two are assumed to be the same outl",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 8,+ "cost_usd": 0.138,+ "at": "2026-10-06T04:02:14"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588902952597114880",+ "pages": 8,+ "sha256": "de730887d826ad0f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 3,+ "described": 3,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}