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Contents

README

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TPDV1240RG

STMicroelectronics · Thyristors (SCR)/Modules · TO-3P-3

TPDV1240RG from STMicroelectronics, in a TO-3P-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 passive Main terminal A1 of the triac, the reference electrode for A2 voltage and gate; insulated tab is isolated to 2,500 V rms from A1, A2 and gate.
2 A2 passive Main terminal A2 of the triac, blocking up to 1200 V (VDRM/VRRM) for TPDV1240RG and carrying 40 A rms on-state current at Tc = 75 °C.
3 G input Gate trigger terminal, IGT max 200 mA and VGT max 1.5 V (VD = 12 V DC, RL = 33 Ω), with peak gate current 8 A for tp = 20 µs.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TO-3P-3
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: TPDV1240RG
  • Footprint: Package_TO_SOT_THT:TO-3P-3_Vertical
  • 3D model: TO-3P-3 (KiCad packages3D, STEP)
  • 3D model files: tpdv1240rg-etched.step / tpdv1240rg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpdv1240rg.step / tpdv1240rg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (8 pp, sha256 de730887d826ad0f, retrieved 2026-10-06, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF