component
TPDRTR5V0U4S
Public Made by Adomby adom
TECH PUBLIC ESD And Surge Protection (TVS/ESD), SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPDRTR5V0U4S
TECH PUBLIC · ESD And Surge Protection (TVS/ESD) · SOT-363
TPDRTR5V0U4S from TECH PUBLIC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IO1 | passive | ESD-protected high-speed I/O channel, protected to IEC 61000-4-2 ±18kV air/±14kV contact with 1.3pF typical capacitance to ground. |
| 2 | GND | power_in | Ground reference of the TVS array; pin 5 to pin 2 is the supply/reverse stand-off path (5V max working voltage). |
| 3 | IO2 | passive | ESD-protected high-speed I/O channel, protected to IEC 61000-4-2 ±18kV air/±14kV contact with 1.3pF typical capacitance to ground. |
| 4 | IO3 | passive | ESD-protected high-speed I/O channel, protected to IEC 61000-4-2 ±18kV air/±14kV contact with 1.3pF typical capacitance to ground. |
| 5 | VDD | power_in | Positive supply/power line protected by the internal TVS, with 5V reverse stand-off, 6V to 9V breakdown at 1mA, and 6V absolute maximum VDD-GND. |
| 6 | IO4 | passive | ESD-protected high-speed I/O channel, protected to IEC 61000-4-2 ±18kV air/±14kV contact with 1.3pF typical capacitance to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-363 |
| Category | Circuit Protection |
| Pins | 6 |
CAD (KiCad official)
- Symbol:
TPDRTR5V0U4S - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files:
tpdrtr5v0u4s-etched.step/tpdrtr5v0u4s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpdrtr5v0u4s.step/tpdrtr5v0u4s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TECH PUBLIC datasheet (4 pp, sha256
889daf5e5bbbfe98, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPDRTR5V0U4S
**TECH PUBLIC** · ESD And Surge Protection (TVS/ESD) · SOT-363
TPDRTR5V0U4S from TECH PUBLIC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IO1 | passive | ESD-protected high-speed I/O channel, protected to IEC 61000-4-2 ±18kV air/±14kV contact with 1.3pF typical capacitance to ground. |
| 2 | GND | power_in | Ground reference of the TVS array; pin 5 to pin 2 is the supply/reverse stand-off path (5V max working voltage). |
| 3 | IO2 | passive | ESD-protected high-speed I/O channel, protected to IEC 61000-4-2 ±18kV air/±14kV contact with 1.3pF typical capacitance to ground. |
| 4 | IO3 | passive | ESD-protected high-speed I/O channel, protected to IEC 61000-4-2 ±18kV air/±14kV contact with 1.3pF typical capacitance to ground. |
| 5 | VDD | power_in | Positive supply/power line protected by the internal TVS, with 5V reverse stand-off, 6V to 9V breakdown at 1mA, and 6V absolute maximum VDD-GND. |
| 6 | IO4 | passive | ESD-protected high-speed I/O channel, protected to IEC 61000-4-2 ±18kV air/±14kV contact with 1.3pF typical capacitance to ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-363 |
| Category | Circuit Protection |
| Pins | 6 |
## CAD (KiCad official)
- Symbol: `TPDRTR5V0U4S`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files: `tpdrtr5v0u4s-etched.step` / `tpdrtr5v0u4s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpdrtr5v0u4s.step` / `tpdrtr5v0u4s.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590183075297992704) (4 pp, sha256 `889daf5e5bbbfe98`, retrieved 2026-10-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tpdrtr5v0u4s-datasheet.pdf)